From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C77DDA0545; Tue, 20 Dec 2022 20:29:45 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F329F42D9B; Tue, 20 Dec 2022 20:27:20 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A04C342D35 for ; Tue, 20 Dec 2022 20:27:01 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BKHPQ0w015491 for ; Tue, 20 Dec 2022 11:27:00 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=4S7y8JT9Yj53rGSDDjkHco0CxPJJOsA/pPCMLIE+n+k=; b=XQP9kxZtxUOXGVPHDZs2dYYgoOwQKm0dDk6jSeDyYH6WMnw2CIp/Pii+9B3iu1FMiOUX 2UIyFOJbXtCcPVd/y9IjTDWSL+vnJUH0QbtOXk+3N6H3XDJnBpw2PNOlHyihoR1V0f5n dNAtRR+HWaK7TAq0q04m9ojb90Mjajrw4RfWQ91Av/JwEj1mzL1fPMe+Rb78eijUXmz6 bxduBisM3rySrxlqPFoMvuJEA+C8gf4r2swOb1AdOizVZUKlH/65Lua3Ux1OBOW/3cVk geLAaSj9FH5le7rgAwPeJb8qVIK+3EckqUrUpwATiLnlr8nWL8fV93tPYLmS2Q4DhXnZ 9Q== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mkapj2tq2-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 20 Dec 2022 11:27:00 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 20 Dec 2022 11:26:59 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 20 Dec 2022 11:26:59 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id CD88D3F7051; Tue, 20 Dec 2022 11:26:58 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , Subject: [PATCH v3 27/38] ml/cnxk: dequeue a burst of inference requests Date: Tue, 20 Dec 2022 11:26:34 -0800 Message-ID: <20221220192645.14042-28-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221220192645.14042-1-syalavarthi@marvell.com> References: <20221208201806.21893-1-syalavarthi@marvell.com> <20221220192645.14042-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: W6_coScrv7E_nIx8wcnRMMzlTq8V8HSt X-Proofpoint-GUID: W6_coScrv7E_nIx8wcnRMMzlTq8V8HSt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-20_06,2022-12-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enabled driver support to dequeue inference requests from internal queue. Dequeue checks for request completion by polling the status field of the job request. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_ops.c | 61 ++++++++++++++++++++++++++++++++++ drivers/ml/cnxk/cn10k_ml_ops.h | 2 ++ 2 files changed, 63 insertions(+) diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index e6bfc6635e..8de2b3e49c 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -473,6 +473,7 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c rte_spinlock_init(&ocm->lock); dev->enqueue_burst = cn10k_ml_enqueue_burst; + dev->dequeue_burst = cn10k_ml_dequeue_burst; mldev->nb_models_loaded = 0; mldev->state = ML_CN10K_DEV_STATE_CONFIGURED; @@ -1417,6 +1418,23 @@ queue_free_count(uint64_t head, uint64_t tail, uint64_t nb_desc) return nb_desc - queue_pending_count(head, tail, nb_desc) - 1; } +static __rte_always_inline void +cn10k_ml_result_update(struct rte_ml_dev *dev, int qp_id, struct cn10k_ml_result *result, + struct rte_ml_op *op) +{ + PLT_SET_USED(dev); + PLT_SET_USED(qp_id); + + op->impl_opaque = result->error_code; + + if (likely(result->error_code == 0)) + op->status = RTE_ML_OP_STATUS_SUCCESS; + else + op->status = RTE_ML_OP_STATUS_ERROR; + + op->user_ptr = result->user_ptr; +} + __rte_hot uint16_t cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op **ops, uint16_t nb_ops) @@ -1471,6 +1489,49 @@ cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op return count; } +__rte_hot uint16_t +cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op **ops, + uint16_t nb_ops) +{ + struct cn10k_ml_queue *queue; + struct cn10k_ml_req *req; + struct cn10k_ml_qp *qp; + + uint64_t status; + uint16_t count; + uint64_t tail; + + qp = dev->data->queue_pairs[qp_id]; + queue = &qp->queue; + + tail = queue->tail; + nb_ops = PLT_MIN(nb_ops, queue_pending_count(queue->head, tail, qp->nb_desc)); + count = 0; + + if (unlikely(nb_ops == 0)) + goto empty_or_active; + +dequeue_req: + req = &queue->reqs[tail]; + status = plt_read64(&req->status); + if (unlikely(status != ML_CN10K_POLL_JOB_FINISH)) + goto empty_or_active; + + cn10k_ml_result_update(dev, qp_id, &req->result, req->op); + ops[count] = req->op; + + queue_index_advance(&tail, qp->nb_desc); + count++; + + if (count < nb_ops) + goto dequeue_req; + +empty_or_active: + queue->tail = tail; + + return count; +} + struct rte_ml_dev_ops cn10k_ml_ops = { /* Device control ops */ .dev_info_get = cn10k_ml_dev_info_get, diff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h index d35f91a302..3178295bba 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.h +++ b/drivers/ml/cnxk/cn10k_ml_ops.h @@ -73,5 +73,7 @@ int cn10k_ml_model_stop(struct rte_ml_dev *dev, int16_t model_id); /* Fast-path ops */ __rte_hot uint16_t cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op **ops, uint16_t nb_ops); +__rte_hot uint16_t cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, + struct rte_ml_op **ops, uint16_t nb_ops); #endif /* _CN10K_ML_OPS_H_ */ -- 2.17.1