From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 25D6FA0545; Tue, 20 Dec 2022 20:29:51 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0F95042D9F; Tue, 20 Dec 2022 20:27:22 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 055B042D33 for ; Tue, 20 Dec 2022 20:27:01 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BKHPQ0x015491 for ; Tue, 20 Dec 2022 11:27:01 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=8b4lC1VRvF5Hu6A1ccUZMci6pZfF+MUgA+BN5Bmmpjg=; b=fY1wxvB9DM5B2I+T3C1WOyXmHghYNpDXqXj2V5UfCvpIsD+iJxpDR/rNSiUHUeymvlzj JZe7NrwrZHK0y3DCBkwcZEZslXW1tXW+OxoQqEiq+DjZzvJu+w5SVxDiAcKuGyyVceCF 0iZifbaAbXKwviYOvcS3gK3OTkcaM3KNS1HwfFiGOnrJtP68zSPqTmV6TpZvQxrMNPMI HTHvu+WYtOHEw8N+JieSPMUVPY8GmOYJf6dbMs8YEH/tc5gCkABTuADXj1TDFu+8vgmM OF/2ENGIR8Y8nDKIz573FhwRH6RhQj1WTQItLMT3wkvvgrH0gBLBfZ9dQiwLcU4ysFo/ IA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mkapj2tq2-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 20 Dec 2022 11:27:01 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 20 Dec 2022 11:26:59 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 20 Dec 2022 11:26:59 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 252B03F7070; Tue, 20 Dec 2022 11:26:59 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , Subject: [PATCH v3 28/38] ml/cnxk: add internal function for sync mode run Date: Tue, 20 Dec 2022 11:26:35 -0800 Message-ID: <20221220192645.14042-29-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221220192645.14042-1-syalavarthi@marvell.com> References: <20221208201806.21893-1-syalavarthi@marvell.com> <20221220192645.14042-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: t_8THPfKI1FeN5O8Y2WRhGzOh67q5Pz4 X-Proofpoint-GUID: t_8THPfKI1FeN5O8Y2WRhGzOh67q5Pz4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-20_06,2022-12-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added internal function to execute ML inference requests in synchronous mode. Sync mode inference execution is used to launch inference requests without using a queue-pair. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_ops.c | 53 ++++++++++++++++++++++++++++++++++ drivers/ml/cnxk/cn10k_ml_ops.h | 1 + 2 files changed, 54 insertions(+) diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index 8de2b3e49c..61e19f85fb 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -1532,6 +1532,59 @@ cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op return count; } +__rte_hot int +cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op) +{ + struct cn10k_ml_model *model; + struct cn10k_ml_dev *mldev; + struct cn10k_ml_req *req; + bool timeout; + int ret = 0; + + mldev = dev->data->dev_private; + model = dev->data->models[op->model_id]; + req = model->req; + + cn10k_ml_prep_fp_job_descriptor(dev, req, op); + + memset(&req->result, 0, sizeof(struct cn10k_ml_result)); + req->result.user_ptr = op->user_ptr; + + plt_write64(ML_CN10K_POLL_JOB_START, &req->status); + req->jcmd.w1.s.jobptr = PLT_U64_CAST(&req->jd); + + timeout = true; + req->timeout = plt_tsc_cycles() + ML_CN10K_CMD_TIMEOUT * plt_tsc_hz(); + do { + if (roc_ml_jcmdq_enqueue_lf(&mldev->roc, &req->jcmd)) { + req->op = op; + timeout = false; + break; + } + } while (plt_tsc_cycles() < req->timeout); + + if (timeout) { + ret = -EBUSY; + goto error_enqueue; + } + + timeout = true; + do { + if (plt_read64(&req->status) == ML_CN10K_POLL_JOB_FINISH) { + timeout = false; + break; + } + } while (plt_tsc_cycles() < req->timeout); + + if (timeout) + ret = -ETIME; + else + cn10k_ml_result_update(dev, -1, &req->result, req->op); + +error_enqueue: + return ret; +} + struct rte_ml_dev_ops cn10k_ml_ops = { /* Device control ops */ .dev_info_get = cn10k_ml_dev_info_get, diff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h index 3178295bba..a17a2851b1 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.h +++ b/drivers/ml/cnxk/cn10k_ml_ops.h @@ -75,5 +75,6 @@ __rte_hot uint16_t cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id struct rte_ml_op **ops, uint16_t nb_ops); __rte_hot uint16_t cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op **ops, uint16_t nb_ops); +__rte_hot int cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op); #endif /* _CN10K_ML_OPS_H_ */ -- 2.17.1