From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D0074A034C; Wed, 21 Dec 2022 11:30:50 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 674B842D25; Wed, 21 Dec 2022 11:30:43 +0100 (CET) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2056.outbound.protection.outlook.com [40.107.220.56]) by mails.dpdk.org (Postfix) with ESMTP id 4740C42D1F for ; Wed, 21 Dec 2022 11:30:41 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ehtklffkDQoAc41zAYQvXDHAZaLqocokQ9HFe27xKeXWtLXw/icx+9shddrRQe3Tmc3V7pTunLp9pCKOob4DjBMlD/WRRTyT4oDz9Lb7eeApLA0NSwuazneGkyccWxUill9G0sKGA6jofyXZicLz9wcjJDpHO94JrQy/tbEFRDzqofXaWXoclbqwcCAto4Ve2ROnIapg8fcBhiJH3k5yw9v4oa6reHO+i/OSeq3yfC2fkkp9yqn8WeboGQcsnrGtWqChh/58hKsrq0harIpWnDAnmGApSP0sNd3AmNANhKx1hzUmCHBAdXLu+xHMFJrN/kOVZ0A5YT7lguwvSzXv1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=f79Se+pzTHADkvuDkpehyARJjyctL73wUvPZHQOxgjE=; b=AkDAEpDjESiQDmJoSB4GYyBKZBsdGcfrS9u9/Uxzbd48M8820qwgMc0iP6hG2aPHtDJ2VGzq9DX0SLQN/wSm2NlLUBPNeYhcCMhIF4XjvrmwgA/NIMzkWvAOa9a++11tWwf81nhHUaOsNtt3jzC/AOP442wNa7y2LD1sID/XaW+GWv8tp80ZZUeKGETcDO2gFKBTwi71Xw63glYA+HivJFEKKnaFVNawJjhPORROLXSwQLjtcjVcS1Ny2jxjqpGE6Qi4KR1hK8T/ZMxqDmgxGcNP8ZzDShP45pSSsMhM2DL3ZolUFRhAZ39Tyx3p6jNOHm8VVtwYb3xpe40lWuHl7w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=f79Se+pzTHADkvuDkpehyARJjyctL73wUvPZHQOxgjE=; b=bklB89u+ntwL7n+s8Cw/e7zjPKeLuUo+6P12vU9oI97jaTvTCoDdzaRhu8dExuSIb2SjQPlaRRhqhxco0GRzShxDeTKPMULb9JastwQQeNsRoFRp+PxN2BRelGpe+o5r7Ja+jpEIrw9s+/SpDV9ralrq4fp5JJCY/mV+HN9CxseWKtSIF+qC/YxtgkA7sCu/llEgoUenJ/0VdThU7Es+aRrra1EG9xwhLVcvWgnx++DHfHxckI4c6s+Exa08m2psfNJozPS2Aq7T70rryQG2PvxaGmsQj3mLumsHra5UudpCXR9unjxZdrG+/Kfp70HYEKMZdc/zewQ4w+Laj4Ovug== Received: from MW4PR04CA0134.namprd04.prod.outlook.com (2603:10b6:303:84::19) by SJ2PR12MB7797.namprd12.prod.outlook.com (2603:10b6:a03:4c5::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.16; Wed, 21 Dec 2022 10:30:39 +0000 Received: from CO1NAM11FT060.eop-nam11.prod.protection.outlook.com (2603:10b6:303:84:cafe::91) by MW4PR04CA0134.outlook.office365.com (2603:10b6:303:84::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5924.21 via Frontend Transport; Wed, 21 Dec 2022 10:30:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1NAM11FT060.mail.protection.outlook.com (10.13.175.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5944.10 via Frontend Transport; Wed, 21 Dec 2022 10:30:38 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 21 Dec 2022 02:30:23 -0800 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 21 Dec 2022 02:30:21 -0800 From: Jiawei Wang To: , , , "Matan Azrad" CC: , Subject: [RFC 4/5] net/mlx5: add port affinity item support Date: Wed, 21 Dec 2022 12:29:33 +0200 Message-ID: <20221221102934.13822-5-jiaweiw@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221221102934.13822-1-jiaweiw@nvidia.com> References: <20221221102934.13822-1-jiaweiw@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT060:EE_|SJ2PR12MB7797:EE_ X-MS-Office365-Filtering-Correlation-Id: 884a070d-7623-4a3a-f598-08dae33e678c X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Rqzyc9TwxCTJwoSyiIE7Oqvq0paETZ22zZzyelxjLLCaUbiQGXUXcv5tzenMTWOEHuGkdDLG7ZmiAgz8CtEQqVFn84f7tadAdV0U19f4genJjvF/0IWbs4PpfmdEyo1+kgpwUWm86ag3OLBmJJhDrUV87+uxVoXkZbvn2E9LXVaRM0VmCKCZUrLcHZteH5DQwtfxzDVwR6rgwyBZSITpysOBOXhAnRmtXmVVbQSj0XAF6u8pIjhHJTeh6puYK8CvBY8FQH8/K7hAo6ZeZJrXBRYWWJvCxJvBSY4Z9MYnP8dE4Hk7wojUrTpW9Z396ZxLE0W29W+LftePrgom7lPDGeVYUM9CwARJnlu4qpYnsSi+WJ7t05km8CP4ghYbs+A7xhIM0uQ0FmD515IqxojgQ3p15PRfyVgzkBBskJvkvx+shTyX1jcIV06RA8xRwLqmQhk1D6Wr8eri18DLA0vd+SGlmttoZCW14xMxiilJLDa53DykVVaZZ9TKMquZ2Ruez2YKWZIlHapuS3jMpNuZ4q4Zpace1DqpFLiMGUj6hEGRTi8dkdJlOSNqyU8ofpDRDI7kG55R4gllSkgpf9xaCBbaqEFzqd4C2znlQRK/bAmWvJ2gJK45LklKjC68lTPV1+uArmQSlwLNL2r83CgMYSvfh1T7YrzXqLpt8jgvJdu6t1YjVK3EJ7z16Yy7yGw8PtAzjTxm52jEl3TncYt4EA== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(376002)(346002)(136003)(396003)(451199015)(40470700004)(36840700001)(46966006)(2906002)(36756003)(6286002)(6636002)(186003)(26005)(40460700003)(356005)(82310400005)(70206006)(7636003)(110136005)(86362001)(16526019)(70586007)(5660300002)(426003)(1076003)(316002)(41300700001)(8936002)(82740400003)(47076005)(83380400001)(336012)(55016003)(40480700001)(54906003)(8676002)(7696005)(4326008)(2616005)(107886003)(6666004)(478600001)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2022 10:30:38.9552 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 884a070d-7623-4a3a-f598-08dae33e678c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7797 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds the new port affinity item supports in PMD: RTE_FLOW_ITEM_TYPE_PORT_AFFINITY. This patch adds the validation function for the new item, it works for NIC-RX rules on ROOT-table only. Signed-off-by: Jiawei Wang --- doc/guides/nics/features/mlx5.ini | 1 + doc/guides/nics/mlx5.rst | 4 +- drivers/net/mlx5/linux/mlx5_os.c | 2 + drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_flow.h | 3 + drivers/net/mlx5/mlx5_flow_dv.c | 95 +++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 14 +++++ 7 files changed, 119 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini index 62fd330e2b..a7766221c9 100644 --- a/doc/guides/nics/features/mlx5.ini +++ b/doc/guides/nics/features/mlx5.ini @@ -87,6 +87,7 @@ vlan = Y vxlan = Y vxlan_gpe = Y represented_port = Y +port_affinity = Y [rte_flow actions] age = I diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 85a2b422c5..fe33c2a895 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -106,6 +106,7 @@ Features - Sub-Function representors. - Sub-Function. - Matching on represented port. +- Matching on port affinity. Limitations @@ -595,10 +596,11 @@ Limitations - key - sequence - Matching on checksum and sequence needs MLNX_OFED 5.6+. +- Matching on checksum and sequence needs MLNX_OFED 5.6+. - The NIC egress flow rules on representor port are not supported. +- Match on port affinity is supported NIC ingress flow in group 0 only. Statistics ---------- diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 3fea72013f..babc7d2f94 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1406,6 +1406,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, sh->lag_rx_port_affinity_en = 1; DRV_LOG(DEBUG, "LAG Rx Port Affinity enabled"); } + priv->num_lag_ports = hca_attr->num_lag_ports; + DRV_LOG(DEBUG, "The number of lag ports is %d", priv->num_lag_ports); } /* Process parameters and store port configuration on priv structure. */ err = mlx5_port_args_config(priv, mkvlist, &priv->config); diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index dc4d1a8686..52f1592035 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1739,6 +1739,7 @@ struct mlx5_priv { unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ unsigned int lb_used:1; /* Loopback queue is referred to. */ uint32_t mark_enabled:1; /* If mark action is enabled on rxqs. */ + uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ uint16_t domain_id; /* Switch domain identifier. */ uint16_t vport_id; /* Associated VF vport index (if any). */ uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 7148c10e96..13cf9b7d76 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -264,6 +264,9 @@ enum mlx5_feature_name { /* IPSEC syndrome item */ #define MLX5_FLOW_ITEM_IPSEC_SYNDROME (UINT64_C(1) << 46) +/* Port affinity item */ +#define MLX5_FLOW_ITEM_PORT_AFFINITY (UINT64_C(1) << 47) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 310fb7c5c3..62a6fb496d 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -3888,6 +3888,74 @@ flow_dv_validate_item_ipsec_syndrome(struct rte_eth_dev *dev, return 0; } +/** + * Validate Port affinity item. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] item + * Item specification. + * @param[in] attr + * Attributes of flow that includes this item. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +flow_dv_validate_item_port_affinity(struct rte_eth_dev *dev, + const struct rte_flow_item *item, + const struct rte_flow_attr *attr, + struct rte_flow_error *error) +{ + struct mlx5_priv *priv = dev->data->dev_private; + const struct rte_flow_item_port_affinity *spec = item->spec; + const struct rte_flow_item_port_affinity *mask = item->mask; + struct rte_flow_item_port_affinity nic_mask = { + .affinity = UINT8_MAX + }; + int ret; + + if (!priv->sh->lag_rx_port_affinity_en) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "Unsupported port affinity with Older FW"); + if (!attr->ingress || attr->transfer || attr->group) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + item->spec, + "port affinity is supported with NIC-RX on Root"); + if (!spec) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + item->spec, + "data cannot be empty"); + if (spec->affinity == 0) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + item->spec, + "zero affinity number not supported"); + if (spec->affinity > priv->num_lag_ports) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, + item->spec, + "exceed max affinity number in lag ports"); + if (!mask) + mask = &rte_flow_item_port_affinity_mask; + if (!mask->affinity) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL, + "mask cannot be zero"); + ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, + (const uint8_t *)&nic_mask, + sizeof(struct rte_flow_item_port_affinity), + MLX5_ITEM_RANGE_NOT_ACCEPTED, error); + if (ret < 0) + return ret; + return 0; +} + int flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry, void *cb_ctx) @@ -7679,6 +7747,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, return ret; last_item = MLX5_FLOW_ITEM_IPSEC_SYNDROME; break; + case RTE_FLOW_ITEM_TYPE_PORT_AFFINITY: + ret = flow_dv_validate_item_port_affinity(dev, items, + attr, error); + if (ret < 0) + return ret; + last_item = MLX5_FLOW_ITEM_PORT_AFFINITY; + break; default: return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, @@ -10978,6 +11053,22 @@ flow_dv_translate_item_ipsec_syndrome(void *key, spec->syndrome & mask->syndrome); } +static void +flow_dv_translate_item_port_affinity(void *key, + const struct rte_flow_item *item, + uint32_t key_type) +{ + const struct rte_flow_item_port_affinity *affinity_v; + const struct rte_flow_item_port_affinity *affinity_m; + void *misc_v; + + MLX5_ITEM_UPDATE(item, key_type, affinity_v, affinity_m, + &rte_flow_item_port_affinity_mask); + misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters); + MLX5_SET(fte_match_set_misc, misc_v, lag_rx_port_affinity, + affinity_v->affinity & affinity_m->affinity); +} + static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 }; #define HEADER_IS_ZERO(match_criteria, headers) \ @@ -13779,6 +13870,10 @@ flow_dv_translate_items(struct rte_eth_dev *dev, flow_dv_translate_item_ipsec_syndrome(key, items, key_type); last_item = MLX5_FLOW_ITEM_IPSEC_SYNDROME; break; + case RTE_FLOW_ITEM_TYPE_PORT_AFFINITY: + flow_dv_translate_item_port_affinity(key, items, key_type); + last_item = MLX5_FLOW_ITEM_PORT_AFFINITY; + break; default: break; } diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 0705002d99..2e93dcf801 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -5015,6 +5015,20 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, "Unsupported meter color register"); break; } + case RTE_FLOW_ITEM_TYPE_PORT_AFFINITY: + { + if (!priv->sh->lag_rx_port_affinity_en) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "Unsupported port affinity with Older FW"); + if (!attr->ingress || attr->transfer) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "Port affinity item not supported" + " with egress or transfer" + " attribute"); + break; + } case RTE_FLOW_ITEM_TYPE_VOID: case RTE_FLOW_ITEM_TYPE_ETH: case RTE_FLOW_ITEM_TYPE_VLAN: -- 2.18.1