From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8571C42413; Thu, 19 Jan 2023 06:53:29 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1E0D2410DD; Thu, 19 Jan 2023 06:53:29 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 113EF4068E for ; Thu, 19 Jan 2023 06:53:26 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30J2NpNZ014031 for ; Wed, 18 Jan 2023 21:53:26 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=pnJNIAHdIDyZdCg6PhNabIFn4K6GgUlvrWAkjsjgqp8=; b=jGKyX/9WyhnHaTlF5WAgLzaJeTJNQupFGRFHAOAYXExyu0JelTpMHTOHVa1yavrCvOW+ Xau1DE3VVEbev/Bf0iFxsIN7/i0Mwxao217zrn3BoXsoJ/ktqeWWATTTxZygXI19n+oV hWr3UcCCI0TeEiOVVvkIleSsA+BegCYcAboy5fcsaKV8OJkk+IM6IiiuV+sSlJ4nH3uy BQg0D05HLxuLtI1lr8PHnGtVZ7GuVX0BBt/e8iyDjtYDeVlYnyK6ZsuUYImtxIeCyu1t zd9AspWAvigCuY2cW+CP307p6qVYxI4YLfWc61XM01jm+YQLNFI6OB3NDGu7sX5CahQ6 Hw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3n3vstpk9h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 18 Jan 2023 21:53:25 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 18 Jan 2023 21:53:23 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Wed, 18 Jan 2023 21:53:23 -0800 Received: from localhost.localdomain (unknown [10.28.36.158]) by maili.marvell.com (Postfix) with ESMTP id 92F9D3F704C; Wed, 18 Jan 2023 21:53:20 -0800 (PST) From: Rahul Bhansali To: , Pavan Nikhilesh , "Shijith Thotton" , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rahul Bhansali Subject: [PATCH v2] event/cnxk: wait for CPT flow control on WQE path Date: Thu, 19 Jan 2023 11:23:15 +0530 Message-ID: <20230119055315.915251-1-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221209134121.1757306-1-rbhansali@marvell.com> References: <20221209134121.1757306-1-rbhansali@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: CdPxzhYOsOl7A0WKl0lSQxtYf82wXdVV X-Proofpoint-GUID: CdPxzhYOsOl7A0WKl0lSQxtYf82wXdVV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.923,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-18_05,2023-01-18_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This is to avoid CPT queue overflow and thereby a CPT misc interrupt. Fixes: 1a7da795f64 ("net/cnxk: support Tx security offload on cn9k") Signed-off-by: Rahul Bhansali --- Changes in v2: Updated commit message. drivers/event/cnxk/cn9k_worker.h | 1 + drivers/net/cnxk/cn9k_tx.h | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index 54213db3b4..1ce4b044e8 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -730,6 +730,7 @@ cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base, rte_io_wmb(); cn9k_sso_txq_fc_wait(txq); + cn9k_nix_sec_fc_wait_one(txq); /* Write CPT instruction to lmt line */ vst1q_u64(lmt_addr, cmd01); diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h index 17bbdce3a0..b4ef45d65c 100644 --- a/drivers/net/cnxk/cn9k_tx.h +++ b/drivers/net/cnxk/cn9k_tx.h @@ -411,6 +411,16 @@ cn9k_nix_xmit_prep_lmt(uint64_t *cmd, void *lmt_addr, const uint32_t flags) roc_lmt_mov(lmt_addr, cmd, cn9k_nix_tx_ext_subs(flags)); } +static __rte_always_inline void +cn9k_nix_sec_fc_wait_one(const struct cn9k_eth_txq *txq) +{ + uint64_t nb_desc = txq->cpt_desc; + uint64_t *fc = txq->cpt_fc; + + while (nb_desc <= __atomic_load_n(fc, __ATOMIC_RELAXED)) + ; +} + static __rte_always_inline uint64_t cn9k_nix_xmit_submit_lmt(const rte_iova_t io_addr) { -- 2.25.1