From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B40D341C30; Tue, 7 Feb 2023 17:11:12 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8318F42FCC; Tue, 7 Feb 2023 17:08:00 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A085542D16 for ; Tue, 7 Feb 2023 17:07:34 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 317EgVTx017206 for ; Tue, 7 Feb 2023 08:07:33 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=xeAijMZVsgE559mrWl2bAGVKpgMsX1wl/FCZ2hK+wEE=; b=CYJqodLIUGmPvwa+TwC9QmhEnRK6e++Fl2Of2d3HqDOjK0jd6JwL5Us8nEMrDXLiB382 bJUXlHss2qFEGbk6FXw/ZsRxw1k1S6QCH1yMifg2pdbUWpoY7kYSSqZzTeq0LPnRdyYS V1AzdQr8/CuQPilVKrLeiYRkozXLSB/FWJ4iYk+k04sx03M+OVwo81cpMXGAVl7Y0Izt rqkKHGBeWMtTWQETLlohoH3Yzq04l+Pm2Qq9n/kAr+sFBI5oTUW9EyMy1BHVEsrqKWFK eruoNfM7T9i2WBMA+nD4LGbAAsuLZ6mN1RbD6/nX3RUWy3b/cGUXKvDaRNs4cWdpRjNq Dg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3nkdyrssx7-18 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 07 Feb 2023 08:07:33 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 7 Feb 2023 08:07:30 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Tue, 7 Feb 2023 08:07:30 -0800 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id BA91C3F7043; Tue, 7 Feb 2023 08:07:30 -0800 (PST) From: Srikanth Yalavarthi To: Srikanth Yalavarthi CC: , , , , , Subject: [PATCH v5 32/39] ml/cnxk: enable support to get xstats in cycles Date: Tue, 7 Feb 2023 08:07:12 -0800 Message-ID: <20230207160719.1307-33-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230207160719.1307-1-syalavarthi@marvell.com> References: <20221208200220.20267-1-syalavarthi@marvell.com> <20230207160719.1307-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: ISDkCa0tiO3zO-XSrZzqFqAbAU35BN6z X-Proofpoint-GUID: ISDkCa0tiO3zO-XSrZzqFqAbAU35BN6z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-07_07,2023-02-06_03,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enabled support to retrieve xstats in either cycles or ns. Access to sclk is enabled only if an RVU device is probed during initialization. Driver would return the xstats in nanoseconds only when an RVU device is probed, else would fallback to cycles. Signed-off-by: Srikanth Yalavarthi --- drivers/ml/cnxk/cn10k_ml_ops.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index 880bb6a5a9..5689fbfcb2 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -394,6 +394,8 @@ cn10k_ml_model_xstat_get(struct rte_ml_dev *dev, uint16_t model_id, enum cn10k_ml_model_xstats_type type) { struct cn10k_ml_model *model; + uint16_t rclk_freq; /* MHz */ + uint16_t sclk_freq; /* MHz */ uint64_t count = 0; uint64_t value; uint32_t qp_id; @@ -425,6 +427,10 @@ cn10k_ml_model_xstat_get(struct rte_ml_dev *dev, uint16_t model_id, value = 0; } + roc_clk_freq_get(&rclk_freq, &sclk_freq); + if (sclk_freq != 0) /* return in ns */ + value = (value * 1000ULL) / sclk_freq; + return value; } @@ -863,6 +869,8 @@ cn10k_ml_dev_xstats_names_get(struct rte_ml_dev *dev, struct rte_ml_dev_xstats_m struct rte_ml_dev_info dev_info; struct cn10k_ml_model *model; struct cn10k_ml_dev *mldev; + uint16_t rclk_freq; + uint16_t sclk_freq; uint32_t model_id; uint32_t count; uint32_t type; @@ -878,6 +886,7 @@ cn10k_ml_dev_xstats_names_get(struct rte_ml_dev *dev, struct rte_ml_dev_xstats_m /* Model xstats names */ count = 0; cn10k_ml_dev_info_get(dev, &dev_info); + roc_clk_freq_get(&rclk_freq, &sclk_freq); for (id = 0; id < PLT_DIM(cn10k_ml_model_xstats_table) * dev_info.max_models; id++) { model_id = id / PLT_DIM(cn10k_ml_model_xstats_table); @@ -889,8 +898,14 @@ cn10k_ml_dev_xstats_names_get(struct rte_ml_dev *dev, struct rte_ml_dev_xstats_m xstats_map[count].id = id; type = id % PLT_DIM(cn10k_ml_model_xstats_table); - snprintf(xstats_map[count].name, RTE_ML_STR_MAX, "%s-%s-cycles", - model->metadata.model.name, cn10k_ml_model_xstats_table[type].name); + if (sclk_freq == 0) + snprintf(xstats_map[count].name, RTE_ML_STR_MAX, "%s-%s-cycles", + model->metadata.model.name, + cn10k_ml_model_xstats_table[type].name); + else + snprintf(xstats_map[count].name, RTE_ML_STR_MAX, "%s-%s-ns", + model->metadata.model.name, + cn10k_ml_model_xstats_table[type].name); count++; if (count == size) -- 2.17.1