From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4784A41D5F; Fri, 24 Feb 2023 10:41:02 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6C19F42BB1; Fri, 24 Feb 2023 10:40:34 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D03254161A for ; Fri, 24 Feb 2023 10:40:31 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 31O6nQhq032724 for ; Fri, 24 Feb 2023 01:40:31 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Sg0ujwxArllnOhBwOP1bL5V+tOBeY3susLa8FGs75GI=; b=GknjlZ3I/ZY7qG/7YTlGjdzrVAgoqWYJPdnaLIX0vHyBUNPNb+SZHap1Za+t13Dorxry CXtLAawgSFol9/CVSSv/4xphSwYQeYMiA8ncNTzJQy+7feqmb/KFRqcDVn6cqYHvCNVy Kwqh7PBzCfw3sAKSRVrs+3P/CktsNsHnmL58qOJNr+W4/gV0H3/WRYOWJSWQmY9Z79By gFeuAdYlVjS/rsYsujimV9503mwpr2O5uq7VgOvW0vUydLWzbn8wNokfi+V+W5nCikx/ HUoZItbikPONiY/ZpoUpzjPJR/GBZu6dFT5g9YKP3aaAu95Z3/tSa/NXOiRbLaROFWDK Yw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nxfkwb2h9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 24 Feb 2023 01:40:31 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:28 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:28 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 5BF935B692A; Fri, 24 Feb 2023 01:40:27 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Gowrishankar Muthukrishnan , Subject: [PATCH v2 06/11] common/cnxk: ensure flush inval completion with CSR read Date: Fri, 24 Feb 2023 15:10:09 +0530 Message-ID: <20230224094014.3246764-7-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: IwydD0UOwxrT287cIr1DpP9fTlwxyRIj X-Proofpoint-ORIG-GUID: IwydD0UOwxrT287cIr1DpP9fTlwxyRIj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph If a CSR read is issued after a write, the read would block till the write operation is complete. This would help in determining when the FLUSH+INVALIDATE operation is complete. Signed-off-by: Anoob Joseph --- drivers/common/cnxk/hw/cpt.h | 11 +++++++++++ drivers/common/cnxk/roc_cpt.c | 16 ++++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 4 ---- 3 files changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h index d378a4eadd..44ff8b08b2 100644 --- a/drivers/common/cnxk/hw/cpt.h +++ b/drivers/common/cnxk/hw/cpt.h @@ -100,6 +100,17 @@ union cpt_lf_ctx_flush { } s; }; +union cpt_lf_ctx_err { + uint64_t u; + struct { + uint64_t flush_st_flt : 1; + uint64_t busy_flr : 1; + uint64_t busy_sw_flush : 1; + uint64_t reload_faulted : 1; + uint64_t reserved_4_63 : 1; + } s; +}; + union cpt_lf_ctx_reload { uint64_t u; struct { diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index cf514be69f..dff2fbf2a4 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -783,6 +783,7 @@ int roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr, bool inval) { union cpt_lf_ctx_flush reg; + union cpt_lf_ctx_err err; if (lf == NULL) { plt_err("Could not trigger CTX flush"); @@ -795,6 +796,21 @@ roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr, bool inval) plt_write64(reg.u, lf->rbase + CPT_LF_CTX_FLUSH); + plt_atomic_thread_fence(__ATOMIC_ACQ_REL); + + /* Read a CSR to ensure that the FLUSH operation is complete */ + err.u = plt_read64(lf->rbase + CPT_LF_CTX_ERR); + + if (err.s.busy_sw_flush && inval) { + plt_err("CTX entry could not be invalidated due to active usage."); + return -EAGAIN; + } + + if (err.s.flush_st_flt) { + plt_err("CTX flush could not complete due to store fault"); + abort(); + } + return 0; } diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index f03646fe1a..67bd7e3243 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -737,8 +737,6 @@ sym_session_clear(struct rte_cryptodev_sym_session *sess, bool is_session_less) /* Trigger CTX flush + invalidate to remove from CTX_CACHE */ roc_cpt_lf_ctx_flush(sess_priv->lf, &sess_priv->roc_se_ctx.se_ctx, true); - plt_delay_ms(1); - if (sess_priv->roc_se_ctx.auth_key != NULL) plt_free(sess_priv->roc_se_ctx.auth_key); @@ -767,8 +765,6 @@ cnxk_ae_session_clear(struct rte_cryptodev *dev, struct rte_cryptodev_asym_sessi /* Trigger CTX flush + invalidate to remove from CTX_CACHE */ roc_cpt_lf_ctx_flush(priv->lf, &priv->hw_ctx, true); - plt_delay_ms(1); - /* Free resources allocated in session_cfg */ cnxk_ae_free_session_parameters(priv); -- 2.25.1