From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 069D041EAF; Thu, 16 Mar 2023 10:33:48 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EA01F42D0E; Thu, 16 Mar 2023 10:33:47 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 3E7E542D1A for ; Thu, 16 Mar 2023 10:33:46 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32G92hfK011638 for ; Thu, 16 Mar 2023 02:33:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=WIh+oiec87ymrVyJdKynOD024VGblC/sdbuu66Kge6k=; b=jjg0LJ3X4VC1QTQUJTlSH8PJ7S6wNhrwQt/of99B+GQfK5RH9nIcHMOST6xSEiOphUZd u8R6ayeZXq2+CapkUpo+cGLw599kzyGNUlCLhJbHogX7dcb7BgcxQVJwKt4SzDV4ROAQ Nif8DiaP3+vZIja85rSgC3QRg5Yr7RRMbnLxBE0Mda26r9WguVd7CQB2QhYlibDmul+z 6Tl4avLULbNCxrM8S0h2VMzWbggYR/AT3H/WFDoY0LWvhVNVsEmfcxS5FV0w1sRwM0KN B9AbVn7RVj3/k5XQtiZhSQuxvXD4CJOz+U3f1UFgDLqXt/K2oCpIRXsHRtumkm+NrcoG eg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3pbs2u1hxk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 16 Mar 2023 02:33:45 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 16 Mar 2023 02:33:43 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Thu, 16 Mar 2023 02:33:43 -0700 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 15A793F703F; Thu, 16 Mar 2023 02:33:43 -0700 (PDT) From: Srikanth Yalavarthi To: Srikanth Yalavarthi , Prince Takkar , Shivah Shankar S CC: , Subject: [PATCH v2 1/1] ml/cnxk: fix multiple coverity issues Date: Thu, 16 Mar 2023 02:33:41 -0700 Message-ID: <20230316093341.18829-1-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230315135427.11489-1-syalavarthi@marvell.com> References: <20230315135427.11489-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: 3tGEEDAsvPterxFAjQRzzJdofyp8VDKx X-Proofpoint-ORIG-GUID: 3tGEEDAsvPterxFAjQRzzJdofyp8VDKx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-16_06,2023-03-15_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added checks for null pointers. Removed logically dead code. Fix division or modulo by zero. Fix evaluation order violation issues. Fix potential memory leak in xstats function. Coverity issue: 383658 383659, 383664, 383665 Fixes: 817e3e55bb18 ("ml/cnxk: support simulator environment") Fixes: da3325131d71 ("ml/cnxk: find OCM mask and page slots for a model") Fixes: b7d0650ebce0 ("ml/cnxk: reserve and free OCM pages") Fixes: 515e3608c741 ("ml/cnxk: configure OCM page size") Fixes: 4ff4ab8e1a20 ("ml/cnxk: support extended statistics") Signed-off-by: Srikanth Yalavarthi --- v2: * additional null pointer checks * xstats memory leak fix drivers/ml/cnxk/cn10k_ml_dev.c | 4 ++-- drivers/ml/cnxk/cn10k_ml_ocm.c | 39 ++++++++++++---------------------- drivers/ml/cnxk/cn10k_ml_ops.c | 17 +++++++++++++-- 3 files changed, 31 insertions(+), 29 deletions(-) diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c index 6f9a1015a6..bba3c9022e 100644 --- a/drivers/ml/cnxk/cn10k_ml_dev.c +++ b/drivers/ml/cnxk/cn10k_ml_dev.c @@ -779,8 +779,8 @@ cn10k_ml_fw_load(struct cn10k_ml_dev *mldev) if (roc_env_is_emulator() || roc_env_is_hw()) { /* Read firmware image to a buffer */ ret = rte_firmware_read(fw->path, &fw_buffer, &fw_size); - if (ret < 0) { - plt_err("Can't read firmware data: %s\n", fw->path); + if ((ret < 0) || (fw_buffer == NULL)) { + plt_err("Unable to read firmware data: %s\n", fw->path); return ret; } diff --git a/drivers/ml/cnxk/cn10k_ml_ocm.c b/drivers/ml/cnxk/cn10k_ml_ocm.c index d8d2c71a3c..edc1e5dd4b 100644 --- a/drivers/ml/cnxk/cn10k_ml_ocm.c +++ b/drivers/ml/cnxk/cn10k_ml_ocm.c @@ -224,7 +224,6 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w uint16_t scratch_page_start; int used_last_wb_page_max; uint16_t scratch_page_end; - uint8_t search_start_tile; uint8_t search_end_tile; uint8_t *local_ocm_mask; int wb_page_start_curr; @@ -235,7 +234,6 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w uint16_t word_id; uint8_t tile_idx; int max_slot_sz; - int start_tile; int page_id; mldev = dev->data->dev_private; @@ -250,28 +248,18 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w wb_page_start = -1; used_scratch_pages_max = 0; used_last_wb_page_max = -1; - start_tile = -1; max_slot_sz_curr = 0; max_slot_sz = 0; tile_idx = 0; + tile_start = 0; + search_end_tile = ocm->num_tiles - num_tiles; - if ((start_tile != -1) && (start_tile % num_tiles != 0)) { - plt_err("Invalid start_tile, %d", start_tile); + local_ocm_mask = rte_zmalloc("local_ocm_mask", mldev->ocm.mask_words, RTE_CACHE_LINE_SIZE); + if (local_ocm_mask == NULL) { + plt_err("Unable to allocate memory for local_ocm_mask"); return -1; } - if (start_tile < 0) { - search_start_tile = 0; - search_end_tile = ocm->num_tiles - num_tiles; - } else { - search_start_tile = start_tile; - search_end_tile = start_tile; - } - - /* nibbles + prefix '0x' */ - local_ocm_mask = rte_zmalloc("local_ocm_mask", mldev->ocm.mask_words, RTE_CACHE_LINE_SIZE); - - tile_start = search_start_tile; start_search: used_scratch_pages_max = 0; used_last_wb_page_max = -1; @@ -423,10 +411,8 @@ cn10k_ml_ocm_free_pages(struct rte_ml_dev *dev, uint16_t model_id) wb_page_end = wb_page_start + model->model_mem_map.wb_pages - 1; for (tile_id = model->addr.tile_start; tile_id <= model->addr.tile_end; tile_id++) { for (page_id = wb_page_start; page_id <= wb_page_end; page_id++) { - ocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE] = - CLEAR_BIT(ocm->tile_ocm_info[tile_id] - .ocm_mask[page_id / OCM_MAP_WORD_SIZE], - page_id % OCM_MAP_WORD_SIZE); + CLEAR_BIT(ocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE], + page_id % OCM_MAP_WORD_SIZE); } /* Update last_wb_page size */ @@ -452,10 +438,9 @@ cn10k_ml_ocm_free_pages(struct rte_ml_dev *dev, uint16_t model_id) prev_start = ocm->num_pages - ocm->tile_ocm_info[tile_id].scratch_pages; curr_start = ocm->num_pages - scratch_resize_pages; for (page_id = prev_start; page_id < curr_start; page_id++) { - ocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE] = - CLEAR_BIT(ocm->tile_ocm_info[tile_id] - .ocm_mask[page_id / OCM_MAP_WORD_SIZE], - page_id % OCM_MAP_WORD_SIZE); + CLEAR_BIT(ocm->tile_ocm_info[tile_id] + .ocm_mask[page_id / OCM_MAP_WORD_SIZE], + page_id % OCM_MAP_WORD_SIZE); } ocm->tile_ocm_info[tile_id].scratch_pages = scratch_resize_pages; } @@ -497,6 +482,10 @@ cn10k_ml_ocm_print(struct rte_ml_dev *dev, FILE *fp) /* nibbles + prefix '0x' */ str = rte_zmalloc("ocm_mask_str", mldev->ocm.num_pages / 4 + 2, RTE_CACHE_LINE_SIZE); + if (str == NULL) { + plt_err("Unable to allocate memory for ocm_mask_str"); + return; + } fprintf(fp, "OCM State:\n"); for (tile_id = 0; tile_id < ocm->num_tiles; tile_id++) { diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c index 7d5eb97668..4df2ca0e8c 100644 --- a/drivers/ml/cnxk/cn10k_ml_ops.c +++ b/drivers/ml/cnxk/cn10k_ml_ops.c @@ -444,7 +444,8 @@ cn10k_ml_prep_fp_job_descriptor(struct rte_ml_dev *dev, struct cn10k_ml_req *req count += model->burst_stats[qp_id].dequeued_count - \ model->burst_stats[qp_id].str##_reset_count; \ } \ - value = value / count; \ + if (count != 0) \ + value = value / count; \ } while (0) #define ML_MIN_FOREACH_QP(dev, model, qp_id, str, value, count) \ @@ -788,6 +789,11 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c /* Allocate memory for ocm_mask */ ocm->ocm_mask = rte_zmalloc("ocm_mask", ocm->mask_words * ocm->num_tiles, RTE_CACHE_LINE_SIZE); + if (ocm->ocm_mask == NULL) { + plt_err("Unable to allocate memory for OCM mask"); + ret = -ENOMEM; + goto error; + } for (tile_id = 0; tile_id < ocm->num_tiles; tile_id++) { ocm->tile_ocm_info[tile_id].ocm_mask = ocm->ocm_mask + tile_id * ocm->mask_words; @@ -1106,6 +1112,11 @@ cn10k_ml_dev_xstats_by_name_get(struct rte_ml_dev *dev, const char *name, uint16 num_xstats = PLT_DIM(cn10k_ml_model_xstats_table) * mldev->nb_models_loaded; xstats_map = rte_zmalloc("cn10k_ml_xstats_map", sizeof(struct rte_ml_dev_xstats_map) * num_xstats, 0); + if (xstats_map == NULL) { + plt_err("Unable to allocate memory for cn10k_ml_xstats_map"); + return -ENOMEM; + } + cn10k_ml_dev_xstats_names_get(dev, xstats_map, num_xstats); cn10k_ml_dev_info_get(dev, &dev_info); @@ -1117,8 +1128,10 @@ cn10k_ml_dev_xstats_by_name_get(struct rte_ml_dev *dev, const char *name, uint16 } } - if (id == PLT_DIM(cn10k_ml_model_xstats_table) * dev_info.max_models) + if (id == PLT_DIM(cn10k_ml_model_xstats_table) * dev_info.max_models) { + rte_free(xstats_map); return -EINVAL; + } model_id = id / PLT_DIM(cn10k_ml_model_xstats_table); type = id % PLT_DIM(cn10k_ml_model_xstats_table); -- 2.17.1