From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 208144280A; Wed, 22 Mar 2023 10:38:49 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 128CA42686; Wed, 22 Mar 2023 10:38:49 +0100 (CET) Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2086.outbound.protection.outlook.com [40.107.95.86]) by mails.dpdk.org (Postfix) with ESMTP id 82FBB40A84 for ; Wed, 22 Mar 2023 10:38:47 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JTDakexcdw6UuKA/1AYqVSXbv2CwKhBQ876VE40QHnIuFVX5Cdhh8jS/YnyvEM27DYcLeBMrxxZULCYyfU4aKa/cB5QgDOm1xPxga+DJvrKn063nYku1+RbnEU3LgnX+6gUe6K/ObrEqWgNrGLWn21PC8YJqQyPWs6I9qH3gdilV+1MntlKGqlQpVmO92hz3UDjC4SvjI64cRACsNIEMJ7iYAksm64fSB2C7GAvhm0rX2/xZ3Dne+KmPkZCSXMTimroebO/T74IPlg3Ryk1GRn8E7xMBTcCvI3oqrnKECoZf4TCfOXoe+VBOwxqL75Yd04iqrmbBaCxZKqkZAdw3PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=iYpgxFOElYpO+LO35hTgL2MzaYSl69Q6trAIspfARDM=; b=cgZ3fj7VgJC+yv6Rp/5N1qh+UUexRh6gKDIdhvuWUVdu2TUH0KMv8YMLjqxB2W/6Y4wRNrX9DFM3mdg1s3HLZu/S1F+yDZ4RxLGyn4cBIGRO+tfWapw5ryEWqqUH2qTKjGuDHTKNNoK+cr2pVusWD8NO++OBJvJzvxo8kfzi3qXm0QHNSZuX/652ybjs8CiB44c5PAYBtrLEHvaoYywaZ2piyPEKLkkzvTfMPeKlHhIgqiXi+wrZGLrT2BbdR75zo8nDpJ8I55uJya054bVsIFcP2Y83UhthX7lgoRqquKiN9B4zjiTj1PD6fSC+ozjtz2zlEx7nownRMN0Z0u8t/Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iYpgxFOElYpO+LO35hTgL2MzaYSl69Q6trAIspfARDM=; b=boS8u6L+L2Zs8JOwGtm1YmHNM3qBSnLfUIhOcxuS0h/XLpMbzKPwfSkD04+G9o2KaDgntmQ7aw61nUMs91pWgwEiAg7YfwpQ7NApTMlweiKSPFJHPHIgqbJ3/7/NfHP8LRZfvkhWVmijka1kn4e7rFXTISTsc9jI35rVL4l7zu2NMvr/edeWzJRMQJ3NfrkMHbQGzEBoZGzvxUoGhLujAcXEGD7H+4CBvo23u+oX3JRXQal2UwRcTPsPAOz3J3x2fxnO4l8LVS//IWWJcT6sr5RoDyAjfu+p7ToG1Z13gDaiZPfD9LYy9Cldph2nKdoHq02EyNZN4Vwo05wRYL+Ecw== Received: from BN1PR13CA0019.namprd13.prod.outlook.com (2603:10b6:408:e2::24) by IA1PR12MB8077.namprd12.prod.outlook.com (2603:10b6:208:3f4::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.37; Wed, 22 Mar 2023 09:38:45 +0000 Received: from BN8NAM11FT107.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e2:cafe::95) by BN1PR13CA0019.outlook.office365.com (2603:10b6:408:e2::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6222.17 via Frontend Transport; Wed, 22 Mar 2023 09:38:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT107.mail.protection.outlook.com (10.13.176.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6222.17 via Frontend Transport; Wed, 22 Mar 2023 09:38:45 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Wed, 22 Mar 2023 02:38:32 -0700 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 22 Mar 2023 02:38:29 -0700 From: Rongwei Liu To: , , , , CC: Michael Baum , Subject: [PATCH v1 1/2] common/mlx5: fix sample ID backward compatibility Date: Wed, 22 Mar 2023 11:38:14 +0200 Message-ID: <20230322093815.3736701-2-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230322093815.3736701-1-rongweil@nvidia.com> References: <20230322093815.3736701-1-rongweil@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT107:EE_|IA1PR12MB8077:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a067469-a766-46de-5285-08db2ab93b6b X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2Dav/HCruzPpLAOAsjSZ9zG/NMsAKLLA0MCp8zTBnCXjJSwXE6rxtc7d7Vqj/M2/kFRaeQD19sXzP42X4AZ0fLPA38C8EDk1wqaCSLJQRDzVBai58QW4ERed5L/TkWMWzErkHe85sPwssRP/mgq0PhiNTW6nw2/ljvAnr++iaHvj3vUXVKTCUvekaIT+XtdxAVt+uvlH1C8u1xb3s3qS8eKdURNMIhC7xBtf83pCEUE0NkfrF1BJKU9m2wQG4C7D3miQnc4xAekcE8TZrmCQts28f2YLMj5Z0HZyRz4mCOw5zX+a1PkmOLvpAoAuD7NvFXXhoZeM0C0u+eRkyfmfYPX56po0yxEDWUKmgUJXTQFTJrEvk/K+QSGYENzhQM53N2VC8Hq4Wj/FNFTBffA9x2r0mFZwlcf/7w94GZE1urw4pq1XAYryfr6XMrJGkZETFqef+0YColXY5uRKQerrEhXDAAbSlKkqEL7xpb2OWB6+tGRknmzjePcgCdObhxTp0OuyIRSErir7OnSfqrtQnAvyrWZFJ9zasGsdR0Hbv7Om1jLuah/dhDwXN4B3iPrAH6E1dXG+N8FS1FVofl88HkPD6lYy3Lq+WLphW1+axj4XWRdpElmi1/XrUwE2dLynROQIC8H8c24FwSmJQ7mvmiMWrNaeY1c1eZfzZ1Sri7ps7GsQSPwth8pgICAaJk/KDzvObjj6lkbFO0APzUGVllvu6ExPjwxFnw/KIrz966yZspBG0lAZF0Q32PAlkleR X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(136003)(376002)(346002)(39860400002)(396003)(451199018)(36840700001)(46966006)(40470700004)(478600001)(6666004)(7696005)(426003)(16526019)(47076005)(107886003)(186003)(6286002)(336012)(26005)(1076003)(83380400001)(54906003)(110136005)(316002)(2616005)(8676002)(70206006)(70586007)(4326008)(36860700001)(5660300002)(41300700001)(8936002)(82740400003)(40460700003)(2906002)(7636003)(55016003)(40480700001)(356005)(36756003)(82310400005)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Mar 2023 09:38:45.5231 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a067469-a766-46de-5285-08db2ab93b6b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8077 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Michael Baum The sample ID of parse graph should be treated as a single value. Add support for new query operation "QUERY_MATCH_SAMPLE_INFO". This operation provides sample information for parse graph sample. DevX commands are only available when dv_flow_en is not zero. Fixes: f1324a171aac ("net/mlx5: adopt IPv6 routing extension PRM definition") Cc: rongweil@nvidia.com Signed-off-by: Michael Baum Signed-off-by: Rongwei Liu --- drivers/common/mlx5/mlx5_devx_cmds.c | 58 ++++++++++++++++++++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 18 ++++++++- drivers/common/mlx5/mlx5_prm.h | 29 +++++++++++++- drivers/common/mlx5/version.map | 1 + 4 files changed, 104 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 580a2ff4f6..86bc183679 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -605,6 +605,62 @@ mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, } } +/** + * Query match sample handle parameters. + * + * This command allows translating a field sample handle returned by either + * PARSE_GRAPH_FLOW_MATCH_SAMPLE or by GENEVE TLV OPTION object into values + * used for header modification or header matching/hashing. + * + * @param[in] ctx + * Context used to create either GENEVE TLV option or FLEX PARSE GRAPH object. + * @param[in] sample_field_id + * Field sample handle returned by either PARSE_GRAPH_FLOW_MATCH_SAMPLE + * or by GENEVE TLV OPTION object. + * @param[out] attr + * Pointer to match sample info attributes structure. + * + * @return + * 0 on success, a negative errno otherwise and rte_errno is set. + */ +int +mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, + struct mlx5_devx_match_sample_info_query_attr *attr) +{ +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + uint32_t out[MLX5_ST_SZ_DW(query_match_sample_info_out)] = {0}; + uint32_t in[MLX5_ST_SZ_DW(query_match_sample_info_in)] = {0}; + int rc; + + MLX5_SET(query_match_sample_info_in, in, opcode, + MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO); + MLX5_SET(query_match_sample_info_in, in, op_mod, 0); + MLX5_SET(query_match_sample_info_in, in, sample_field_id, + sample_field_id); + rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); + if (rc) { + DRV_LOG(ERR, "Failed to query match sample info using DevX: %s", + strerror(rc)); + rte_errno = rc; + return -rc; + } + attr->modify_field_id = MLX5_GET(query_match_sample_info_out, out, + modify_field_id); + attr->sample_dw_data = MLX5_GET(query_match_sample_info_out, out, + field_format_select_dw); + attr->sample_dw_ok_bit = MLX5_GET(query_match_sample_info_out, out, + ok_bit_format_select_dw); + attr->sample_dw_ok_bit_offset = MLX5_GET(query_match_sample_info_out, + out, ok_bit_offset); + return 0; +#else + (void)ctx; + (void)sample_field_id; + (void)attr; + return -ENOTSUP; +#endif +} + int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, struct mlx5_ext_sample_id *ids, @@ -1029,6 +1085,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, alloc_flow_counter_pd); attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, flow_counter_access_aso); + attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, + query_match_sample_info); attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, flow_access_aso_opc_mod); if (attr->crypto) { diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 6ee7d81a99..09540d2f5b 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -296,6 +296,7 @@ struct mlx5_hca_attr { uint32_t flow_counter_bulk_log_granularity:5; uint32_t alloc_flow_counter_pd:1; uint32_t flow_counter_access_aso:1; + uint32_t query_match_sample_info:1; uint32_t flow_access_aso_opc_mod:8; uint32_t cross_vhca:1; uint32_t lag_rx_port_affinity:1; @@ -523,7 +524,6 @@ struct mlx5_devx_virtq_attr { uint8_t q_type; }; - struct mlx5_devx_qp_attr { uint32_t pd:24; uint32_t uar_index:24; @@ -551,6 +551,18 @@ struct mlx5_devx_virtio_q_couners_attr { uint32_t invalid_buffer; }; +/* + * Match sample info attributes structure, used by: + * - GENEVE TLV option query. + * - Graph flow match sample query. + */ +struct mlx5_devx_match_sample_info_query_attr { + uint32_t modify_field_id:12; + uint32_t sample_dw_data:8; + uint32_t sample_dw_ok_bit:8; + uint32_t sample_dw_ok_bit_offset:5; +}; + /* * graph flow match sample attributes structure, * used by flex parser operations. @@ -717,6 +729,9 @@ __rte_internal int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, struct mlx5_devx_modify_tir_attr *tir_attr); __rte_internal +int mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, + struct mlx5_devx_match_sample_info_query_attr *attr); +__rte_internal int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, struct mlx5_ext_sample_id ids[], uint32_t num, uint8_t *anchor); @@ -823,4 +838,5 @@ __rte_internal int mlx5_devx_cmd_query_lag(void *ctx, struct mlx5_devx_lag_context *lag_ctx); + #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 4b0a56f4e5..924f8a7258 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1169,6 +1169,7 @@ enum { MLX5_CMD_SET_REGEX_REGISTERS = 0xb06, MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c, + MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO = 0xb13, MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, MLX5_CMD_OP_GENERATE_WQE = 0xb17, }; @@ -1258,6 +1259,31 @@ struct mlx5_ifc_query_flow_counter_in_bits { u8 flow_counter_id[0x20]; }; +struct mlx5_ifc_query_match_sample_info_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + u8 syndrome[0x20]; + u8 reserved_at_40[0x40]; + u8 reserved_at_80[0x4]; + u8 modify_field_id[0xc]; + u8 ok_bit_format_select_dw[0x8]; + u8 field_format_select_dw[0x8]; + u8 reserved_at_a0[0x3]; + u8 ok_bit_offset[0x5]; + u8 reserved_at_a8[0x18]; + u8 reserved_at_c0[0x40]; +}; + +struct mlx5_ifc_query_match_sample_info_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + u8 reserved_at_40[0x60]; + u8 sample_field_id[0x20]; + u8 reserved_at_c0[0x140]; +}; + #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u @@ -1442,7 +1468,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 access_other_hca_roce[0x1]; u8 alloc_flow_counter_pd[0x1]; u8 flow_counter_access_aso[0x1]; - u8 reserved_at_3[0x5]; + u8 query_match_sample_info[0x1]; + u8 reserved_at_4[0x4]; u8 flow_access_aso_opc_mod[0x8]; u8 reserved_at_10[0xf]; u8 vhca_resource_manager[0x1]; diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 03c8ce5593..e05e1aa8c5 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -45,6 +45,7 @@ INTERNAL { mlx5_devx_cmd_flow_counter_query; mlx5_devx_cmd_flow_dump; mlx5_devx_cmd_flow_single_dump; + mlx5_devx_cmd_match_sample_info_query; mlx5_devx_cmd_mkey_create; mlx5_devx_cmd_modify_qp_state; mlx5_devx_cmd_modify_rq; -- 2.27.0