From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C961C4280A; Wed, 22 Mar 2023 10:38:55 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7FCDF42B8E; Wed, 22 Mar 2023 10:38:54 +0100 (CET) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2040.outbound.protection.outlook.com [40.107.244.40]) by mails.dpdk.org (Postfix) with ESMTP id B1CE240A84 for ; Wed, 22 Mar 2023 10:38:52 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hF/PiJrBIGGvjxcR0o9xJ4yhcXNLf9K2U8K/8JooS0DHHM4SNM9+4wbkSJ69i/ZJNP+tM2Edk0GMNqaZQjxUlEb0YhikM4ki5apxnjumHpakP0H21P2ObpHHGWOCmu7IQixiCWL61xOc+zpsMRdZ+D85AlmZDlTqdYaMmoKYYBpXGpJdgLFr3a0swJ+AYhUyKsfb/0ae8TUG/t0+rXmy+LKnSSxAi1BjnrhSJ4qIbxb1jTHCY1zTdTESTaVPPJWSLe54lN7wYAOFy6ZLAOsjA2q/OT3nA7AsaOrYGc/wV8w2LiCwcnven5P30aoqCHjSFWMMR3jwEFF7WsdtUOyFmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MnJcH7a9dZGGs7Fqab8JC0sePSHbWz80iS5EF1puBmk=; b=eZ7LmY6Y7ZwPbuWHxLwrYHMifPNNAzhL+t9hDy030/2Wu2yua/BpWcKuy0boL3MrZUha/b2oH/xiqnt6Ua2pqUTzyndpEIKmPiU0AoDulZBMkCOynyM4ddeKkiBQ1ekMrBFCvD5AJ68qI6sAKPsvYLT5s1UlL6EQBM0ra4OVgpjsq/MJB8RZhc1sK+7iaehrTzHN9QCKBCSigEiy4aza1tqxvpdkDPNYQK1vNKPaJfNk+bhojHtVWtwdgdyTlbKVUYZuTjgstXmCBqQ5MuqxDczD137JhElaMEP6Td422r9+ynL5UHqD/gJG8TsMnN9py//mTFLQE+nNI4+HzRLJWQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MnJcH7a9dZGGs7Fqab8JC0sePSHbWz80iS5EF1puBmk=; b=lEquLTD/CXP6c/PXxcoVkw6Tmmt5InajcOEX9HRP/55fC1qNEANeose8i0AcQ0gTQKfaHtj206m5yyps1zSFLQ6MlbHwnHLLQJk350+43HLCFRVCr5T/J6u4IHbYH05e6qVvQkGbm+GqeUP8Z+pQelPircnUU1qmg7ZVu2yKD5sXPisNgKSUC+NJDBFjzPdnCB5WPICaGEGtwAl4/exTcZa3eGxVEECY1de2xD6JqYfDTfPRl6hkdyc9OkCmHS85nS99vcx2P1IYWOtIMIEDl1mUuWpGkKtK50tIwermgFRsch33x9WZdtkUa/F2OomEQqIPV52hYAAgd48BojGnWQ== Received: from MW4P223CA0009.NAMP223.PROD.OUTLOOK.COM (2603:10b6:303:80::14) by SN7PR12MB6837.namprd12.prod.outlook.com (2603:10b6:806:267::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.37; Wed, 22 Mar 2023 09:38:49 +0000 Received: from CO1NAM11FT029.eop-nam11.prod.protection.outlook.com (2603:10b6:303:80:cafe::3d) by MW4P223CA0009.outlook.office365.com (2603:10b6:303:80::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.37 via Frontend Transport; Wed, 22 Mar 2023 09:38:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1NAM11FT029.mail.protection.outlook.com (10.13.174.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6222.17 via Frontend Transport; Wed, 22 Mar 2023 09:38:49 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Wed, 22 Mar 2023 02:38:34 -0700 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 22 Mar 2023 02:38:32 -0700 From: Rongwei Liu To: , , , , Subject: [PATCH v1 2/2] net/mlx5: adopt new sample ID Date: Wed, 22 Mar 2023 11:38:15 +0200 Message-ID: <20230322093815.3736701-3-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230322093815.3736701-1-rongweil@nvidia.com> References: <20230322093815.3736701-1-rongweil@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT029:EE_|SN7PR12MB6837:EE_ X-MS-Office365-Filtering-Correlation-Id: eb51d12e-7d6e-425f-a5fa-08db2ab93d92 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: S56w8ivLBtOYUL0UX1zW8KqiXujgYalD8isoI9/XCutpKqFcoq4emGRnwxSihRPIMYoEMKTE+XLgU8fwpEOyS6JGp0R5xmh+chxE4rYZ0ESJWxPZLPiK+ZbmhKKr46fdiNRNCS1MnFYQ8HeZCGcveARTiaFOFCmVvJf+ofa1afPZg/uxbRHBnKp4DeOcDtx9C/MNMvU0A4F9SiUzV1FT7S0dBUXzIfMbjBHcSoD6tnBhwIv6aH4RMtxnfjEnT0vCfdtM5vMtxBSl3CfKWXx5uR3xStAc+TOLYDwu0HzV79O5cTe5jXWN27UT9leHxUm4Gs/APmNUPlbbd30f0+a6nTE2kFvsdXBW4NXGeWllEbFOP8ympM2viEBSaDAzF93vYi2hbf5UrJpIXubBqqSvKNb2CPms0C+KTgni1BlqZiuZGRrxW6PqX040Zy6zfZF9yp1pCid+Y+OwWxySYq26fzTVIEXaxHtdSj0/tQHyej10egVsFWKtPZEp6O7HjPLKiQGIUAM7nDv1MK7rrnEieNJjo3NSV50bkaKnMujUm5d+ZJYh1ipg7hKmT4G14ID1JDj1BOocipkcNMTOd9lgnP3vzWVSxrhvusgmwBL9ovL7tq2Vo5vo7Box0rjp7cOzIk1tVaTY3DRuzvmDxbvSuwSnsUPuRF4ckyR6WEbzAoDVRycqh9UN67hAdY6Qfn0kXy7bme9rTMVUB0BHMNB1dwYqurDgDvsX9PTTfIVTZCJwd/H7kEw0DUjW5DShRgEe X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(396003)(136003)(346002)(376002)(39860400002)(451199018)(36840700001)(46966006)(40470700004)(356005)(2616005)(336012)(82740400003)(6666004)(186003)(1076003)(26005)(6286002)(8676002)(16526019)(47076005)(426003)(83380400001)(82310400005)(2906002)(7636003)(478600001)(86362001)(40460700003)(7696005)(316002)(36860700001)(55016003)(30864003)(110136005)(5660300002)(8936002)(70586007)(70206006)(36756003)(41300700001)(40480700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Mar 2023 09:38:49.1832 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eb51d12e-7d6e-425f-a5fa-08db2ab93d92 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6837 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Extended sample ID is the behavior of the current firmware and this change was reverted. In Apr GA, the sample ID will be the same as 22.11 DPDK (0-7). Now, the sample ID returned by mlx5_devx_cmd_query_parse_samples() is still 0-7 and can be used directly by legacy SWS logic. For HWS, the application should refer to the attributes returned by mlx5_devx_cmd_query_match_sample_info to get the sample_dw_data/ modify_field_id/sample_dw_ok_bit/sample_dw_ok_bit_offset. Signed-off-by: Rongwei Liu --- drivers/common/mlx5/mlx5_devx_cmds.c | 35 +++++++------- drivers/common/mlx5/mlx5_devx_cmds.h | 7 ++- drivers/common/mlx5/mlx5_prm.h | 22 +-------- drivers/net/mlx5/mlx5.c | 71 ++++++++++++++++------------ drivers/net/mlx5/mlx5.h | 20 ++++---- drivers/net/mlx5/mlx5_flow.h | 9 ++-- drivers/net/mlx5/mlx5_flow_dv.c | 8 ++-- drivers/net/mlx5/mlx5_flow_flex.c | 19 ++++---- 8 files changed, 92 insertions(+), 99 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 86bc183679..d0907fcd49 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -663,7 +663,7 @@ mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, - struct mlx5_ext_sample_id *ids, + uint32_t *ids, uint32_t num, uint8_t *anchor) { uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; @@ -695,7 +695,7 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, } if (anchor) *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); - for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx <= num; i++) { + for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx < num; i++) { void *s_off = (void *)((char *)sample + i * MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); uint32_t en; @@ -704,8 +704,8 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, flow_match_sample_en); if (!en) continue; - ids[idx++].id = MLX5_GET(parse_graph_flow_match_sample, s_off, - flow_match_sample_field_id); + ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, + flow_match_sample_field_id); } if (num != idx) { rte_errno = EINVAL; @@ -853,8 +853,7 @@ mlx5_devx_cmd_query_hca_parse_graph_node_cap max_num_arc_out); attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, max_num_sample); - attr->anchor_en = MLX5_GET(parse_graph_node_cap, hcattr, anchor_en); - attr->ext_sample_id = MLX5_GET(parse_graph_node_cap, hcattr, ext_sample_id); + attr->parse_graph_anchor = MLX5_GET(parse_graph_node_cap, hcattr, parse_graph_anchor); attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, sample_tunnel_inner2); attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, @@ -1085,10 +1084,20 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, alloc_flow_counter_pd); attr->flow_counter_access_aso = MLX5_GET(cmd_hca_cap, hcattr, flow_counter_access_aso); - attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, - query_match_sample_info); attr->flow_access_aso_opc_mod = MLX5_GET(cmd_hca_cap, hcattr, flow_access_aso_opc_mod); + /* + * Flex item support needs max_num_prog_sample_field + * from the Capabilities 2 table for PARSE_GRAPH_NODE + */ + if (attr->parse_graph_flex_node) { + rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap + (ctx, &attr->flex); + if (rc) + return -1; + attr->flex.query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, + query_match_sample_info); + } if (attr->crypto) { attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || MLX5_GET(cmd_hca_cap, hcattr, aes_xts_multi_block_be_tweak) || @@ -1172,16 +1181,6 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, log_max_num_meter_aso); } } - /* - * Flex item support needs max_num_prog_sample_field - * from the Capabilities 2 table for PARSE_GRAPH_NODE - */ - if (attr->parse_graph_flex_node) { - rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap - (ctx, &attr->flex); - if (rc) - return -1; - } if (attr->vdpa.valid) mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); if (!attr->eth_net_offloads) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 09540d2f5b..ce173bc36a 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -114,8 +114,8 @@ struct mlx5_hca_flex_attr { uint8_t max_num_arc_out; uint8_t max_num_sample; uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ - uint8_t anchor_en:1; - uint8_t ext_sample_id:1; + uint8_t parse_graph_anchor:1; + uint8_t query_match_sample_info:1; /* Support DevX query sample info. */ uint8_t sample_tunnel_inner2:1; uint8_t zero_size_supported:1; uint8_t sample_id_in_out:1; @@ -296,7 +296,6 @@ struct mlx5_hca_attr { uint32_t flow_counter_bulk_log_granularity:5; uint32_t alloc_flow_counter_pd:1; uint32_t flow_counter_access_aso:1; - uint32_t query_match_sample_info:1; uint32_t flow_access_aso_opc_mod:8; uint32_t cross_vhca:1; uint32_t lag_rx_port_affinity:1; @@ -733,7 +732,7 @@ int mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, struct mlx5_devx_match_sample_info_query_attr *attr); __rte_internal int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, - struct mlx5_ext_sample_id ids[], + uint32_t *ids, uint32_t num, uint8_t *anchor); __rte_internal diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 924f8a7258..4fb1930071 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1975,8 +1975,8 @@ struct mlx5_ifc_parse_graph_node_cap_bits { u8 max_num_arc_out[0x08]; u8 max_num_sample[0x08]; u8 reserved_at_78[0x03]; - u8 anchor_en[0x1]; - u8 ext_sample_id[0x1]; + u8 parse_graph_anchor[0x1]; + u8 reserved_at_7c[0x01]; u8 sample_tunnel_inner2[0x1]; u8 zero_size_supported[0x1]; u8 sample_id_in_out[0x1]; @@ -1988,24 +1988,6 @@ struct mlx5_ifc_parse_graph_node_cap_bits { u8 header_length_mask_width[0x08]; }; -/* ext_sample_id structure, see PRM Table: Flow Match Sample ID Format. */ -struct mlx5_ext_sample_id { - union { - struct { -#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN - uint32_t format_select_dw:8; - uint32_t modify_field_id:12; - uint32_t sample_id:12; -#else - uint32_t sample_id:12; - uint32_t modify_field_id:12; - uint32_t format_select_dw:8; -#endif - }; - uint32_t id; - }; -}; - struct mlx5_ifc_flow_table_prop_layout_bits { u8 ft_support[0x1]; u8 flow_tag[0x1]; diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 41b1b12b91..f24e20a2ef 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -966,12 +966,11 @@ int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; struct mlx5_devx_graph_node_attr node = { .modify_field_select = 0, }; - struct mlx5_ext_sample_id ids[8]; + uint32_t ids[8]; int ret; if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { @@ -1010,18 +1009,16 @@ mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, NULL); if (ret) { DRV_LOG(ERR, "Failed to query sample IDs."); - return (rte_errno == 0) ? -ENODEV : -rte_errno; + goto error; } prf->offset[0] = 0x0; prf->offset[1] = sizeof(uint32_t); - if (attr->ext_sample_id) { - prf->ids[0] = ids[0].sample_id; - prf->ids[1] = ids[1].sample_id; - } else { - prf->ids[0] = ids[0].id; - prf->ids[1] = ids[1].id; - } + prf->ids[0] = ids[0]; + prf->ids[1] = ids[1]; return 0; +error: + mlx5_devx_cmd_destroy(prf->obj); + return (rte_errno == 0) ? -ENODEV : -rte_errno; } /* @@ -1057,20 +1054,24 @@ mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) struct mlx5_devx_graph_node_attr node = { .modify_field_select = 0, }; - struct mlx5_ext_sample_id ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; + uint32_t ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_common_dev_config *config = &priv->sh->cdev->config; - void *ibv_ctx = priv->sh->cdev->ctx; + void *fp = NULL, *ibv_ctx = priv->sh->cdev->ctx; int ret; memset(ids, 0xff, sizeof(ids)); - if (!config->hca_attr.parse_graph_flex_node) { - DRV_LOG(ERR, "Dynamic flex parser is not supported"); + if (!config->hca_attr.parse_graph_flex_node || + !config->hca_attr.flex.query_match_sample_info) { + DRV_LOG(ERR, "Dynamic flex parser is not supported on HWS"); return -ENOTSUP; } if (__atomic_add_fetch(&priv->sh->srh_flex_parser.refcnt, 1, __ATOMIC_RELAXED) > 1) return 0; - + priv->sh->srh_flex_parser.flex.devx_fp = mlx5_malloc(MLX5_MEM_ZERO, + sizeof(struct mlx5_flex_parser_devx), 0, SOCKET_ID_ANY); + if (!priv->sh->srh_flex_parser.flex.devx_fp) + return -ENOMEM; node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIELD; /* Srv6 first two DW are not counted in. */ node.header_length_base_value = 0x8; @@ -1086,28 +1087,41 @@ mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) node.sample[0].flow_match_sample_en = 1; /* First come first serve no matter inner or outer. */ node.sample[0].flow_match_sample_tunnel_mode = MLX5_GRAPH_SAMPLE_TUNNEL_FIRST; + node.sample[0].flow_match_sample_offset_mode = MLX5_GRAPH_SAMPLE_OFFSET_FIXED; node.out[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_TCP; node.out[0].compare_condition_value = IPPROTO_TCP; node.out[1].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_UDP; node.out[1].compare_condition_value = IPPROTO_UDP; node.out[2].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IPV6; node.out[2].compare_condition_value = IPPROTO_IPV6; - priv->sh->srh_flex_parser.fp = mlx5_devx_cmd_create_flex_parser(ibv_ctx, &node); - if (!priv->sh->srh_flex_parser.fp) { + fp = mlx5_devx_cmd_create_flex_parser(ibv_ctx, &node); + if (!fp) { DRV_LOG(ERR, "Failed to create flex parser node object."); - return (rte_errno == 0) ? -ENODEV : -rte_errno; + goto error; } - priv->sh->srh_flex_parser.num = 1; - ret = mlx5_devx_cmd_query_parse_samples(priv->sh->srh_flex_parser.fp, ids, - priv->sh->srh_flex_parser.num, - &priv->sh->srh_flex_parser.anchor_id); + priv->sh->srh_flex_parser.flex.devx_fp->devx_obj = fp; + priv->sh->srh_flex_parser.flex.mapnum = 1; + priv->sh->srh_flex_parser.flex.devx_fp->num_samples = 1; + + ret = mlx5_devx_cmd_query_parse_samples(fp, ids, priv->sh->srh_flex_parser.flex.mapnum, + &priv->sh->srh_flex_parser.flex.devx_fp->anchor_id); if (ret) { DRV_LOG(ERR, "Failed to query sample IDs."); - return (rte_errno == 0) ? -ENODEV : -rte_errno; + goto error; + } + ret = mlx5_devx_cmd_match_sample_info_query(ibv_ctx, ids[0], + &priv->sh->srh_flex_parser.flex.devx_fp->sample_info[0]); + if (ret) { + DRV_LOG(ERR, "Failed to query sample id information."); + goto error; } - priv->sh->srh_flex_parser.offset[0] = 0x0; - priv->sh->srh_flex_parser.ids[0].id = ids[0].id; return 0; +error: + if (fp) + mlx5_devx_cmd_destroy(fp); + if (priv->sh->srh_flex_parser.flex.devx_fp) + mlx5_free(priv->sh->srh_flex_parser.flex.devx_fp); + return (rte_errno == 0) ? -ENODEV : -rte_errno; } /* @@ -1125,10 +1139,9 @@ mlx5_free_srh_flex_parser(struct rte_eth_dev *dev) if (__atomic_sub_fetch(&fp->refcnt, 1, __ATOMIC_RELAXED)) return; - if (fp->fp) - mlx5_devx_cmd_destroy(fp->fp); - fp->fp = NULL; - fp->num = 0; + mlx5_devx_cmd_destroy(fp->flex.devx_fp->devx_obj); + mlx5_free(fp->flex.devx_fp); + fp->flex.devx_fp = NULL; } uint32_t diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 6ad8a42df6..9eae692037 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -545,17 +545,6 @@ struct mlx5_counter_stats_raw { volatile struct flow_counter_stats *data; }; -/* Mlx5 internal flex parser profile structure. */ -struct mlx5_internal_flex_parser_profile { - uint32_t num;/* Actual number of samples. */ - /* Sample IDs for this profile. */ - struct mlx5_ext_sample_id ids[MLX5_FLEX_ITEM_MAPPING_NUM]; - uint32_t offset[MLX5_FLEX_ITEM_MAPPING_NUM]; /* Each ID sample offset. */ - uint8_t anchor_id; - uint32_t refcnt; - void *fp; /* DevX flex parser object. */ -}; - TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); /* Counter global management structure. */ @@ -1323,7 +1312,8 @@ struct mlx5_flex_parser_devx { uint8_t anchor_id; void *devx_obj; struct mlx5_devx_graph_node_attr devx_conf; - struct mlx5_ext_sample_id sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; + uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; + struct mlx5_devx_match_sample_info_query_attr sample_info[MLX5_GRAPH_NODE_SAMPLE_NUM]; }; /* Pattern field descriptor - how to translate flex pattern into samples. */ @@ -1344,6 +1334,12 @@ struct mlx5_flex_item { struct mlx5_flex_pattern_field map[MLX5_FLEX_ITEM_MAPPING_NUM]; }; +/* Mlx5 internal flex parser profile structure. */ +struct mlx5_internal_flex_parser_profile { + uint32_t refcnt; + struct mlx5_flex_item flex; /* Hold map info for modify field. */ +}; + struct mlx5_send_to_kernel_action { void *action; void *tbl; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 9e1e1b975d..1d116ea0f6 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2651,13 +2651,14 @@ flow_hw_get_srh_flex_parser_byte_off_from_ctx(void *dr_ctx __rte_unused) MLX5_ETH_FOREACH_DEV(port, NULL) { struct mlx5_priv *priv; struct mlx5_hca_flex_attr *attr; + struct mlx5_devx_match_sample_info_query_attr *info; priv = rte_eth_devices[port].data->dev_private; attr = &priv->sh->cdev->config.hca_attr.flex; - if (priv->dr_ctx == dr_ctx && attr->ext_sample_id) { - if (priv->sh->srh_flex_parser.num) - return priv->sh->srh_flex_parser.ids[0].format_select_dw * - sizeof(uint32_t); + if (priv->dr_ctx == dr_ctx && attr->query_match_sample_info) { + info = &priv->sh->srh_flex_parser.flex.devx_fp->sample_info[0]; + if (priv->sh->srh_flex_parser.flex.mapnum) + return info->sample_dw_data * sizeof(uint32_t); else return UINT32_MAX; } diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index ca26f39f2b..f136f43b0a 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1457,7 +1457,7 @@ mlx5_modify_flex_item(const struct rte_eth_dev *dev, struct field_modify_info tmp; int tmp_id; - if (!attr->ext_sample_id) { + if (!attr->query_match_sample_info) { DRV_LOG(ERR, "FW doesn't support modify field with flex item."); return; } @@ -1505,8 +1505,8 @@ mlx5_modify_flex_item(const struct rte_eth_dev *dev, tmp_id >= (int)flex->devx_fp->num_samples || tmp_id >= MLX5_GRAPH_NODE_SAMPLE_NUM) return; - if (flex->devx_fp->sample_ids[id].id != - flex->devx_fp->sample_ids[tmp_id].id || + if (flex->devx_fp->sample_info[id].modify_field_id != + flex->devx_fp->sample_info[tmp_id].modify_field_id || flex->map[j].shift != flex->map[j - 1].width + flex->map[j - 1].shift) { i = j; @@ -1532,7 +1532,7 @@ mlx5_modify_flex_item(const struct rte_eth_dev *dev, info[idx] = (struct field_modify_info){cur_width / CHAR_BIT, offset / CHAR_BIT, id == -1 ? MLX5_MODI_INVALID : (enum mlx5_modification_field) - flex->devx_fp->sample_ids[id].modify_field_id, + flex->devx_fp->sample_info[id].modify_field_id, map->shift + tmp_ofs, 1}; offset += cur_width; width_left -= cur_width; diff --git a/drivers/net/mlx5/mlx5_flow_flex.c b/drivers/net/mlx5/mlx5_flow_flex.c index aa317fc958..b527f4178c 100644 --- a/drivers/net/mlx5/mlx5_flow_flex.c +++ b/drivers/net/mlx5/mlx5_flow_flex.c @@ -280,7 +280,7 @@ mlx5_flex_get_parser_value_per_byte_off(const struct rte_flow_item_flex *item, continue; if (id >= (int)tp->devx_fp->num_samples || id >= MLX5_GRAPH_NODE_SAMPLE_NUM) return -1; - if (byte_off == tp->devx_fp->sample_ids[id].format_select_dw * sizeof(uint32_t)) { + if (byte_off == tp->devx_fp->sample_info[id].sample_dw_data * sizeof(uint32_t)) { val = mlx5_flex_get_bitfield(item, pos, map->width, map->shift); if (is_mask) val &= RTE_BE32(def); @@ -319,8 +319,6 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_4); void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4); - struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; struct mlx5_flex_item *tp; uint32_t i, pos = 0; uint32_t sample_id; @@ -330,7 +328,6 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, spec = item->spec; mask = item->mask; tp = (struct mlx5_flex_item *)spec->handle; - MLX5_ASSERT(mlx5_flex_index(priv, tp) >= 0); for (i = 0; i < tp->mapnum; i++) { struct mlx5_flex_pattern_field *map = tp->map + i; uint32_t val, msk, def; @@ -344,10 +341,7 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, return; val = mlx5_flex_get_bitfield(spec, pos, map->width, map->shift); msk = mlx5_flex_get_bitfield(mask, pos, map->width, map->shift); - if (attr->ext_sample_id) - sample_id = tp->devx_fp->sample_ids[id].sample_id; - else - sample_id = tp->devx_fp->sample_ids[id].id; + sample_id = tp->devx_fp->sample_ids[id]; mlx5_flex_set_match_sample(misc4_m, misc4_v, def, msk & def, val & msk & def, sample_id, id); @@ -1391,6 +1385,8 @@ mlx5_flex_parser_create_cb(void *list_ctx, void *ctx) { struct mlx5_dev_ctx_shared *sh = list_ctx; struct mlx5_flex_parser_devx *fp, *conf = ctx; + uint32_t i; + uint8_t sample_info = sh->cdev->config.hca_attr.flex.query_match_sample_info; int ret; fp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct mlx5_flex_parser_devx), @@ -1412,6 +1408,13 @@ mlx5_flex_parser_create_cb(void *list_ctx, void *ctx) &fp->anchor_id); if (ret) goto error; + /* Query sample information per ID. */ + for (i = 0; i < fp->num_samples && sample_info; i++) { + ret = mlx5_devx_cmd_match_sample_info_query(sh->cdev->ctx, fp->sample_ids[i], + &fp->sample_info[i]); + if (ret) + goto error; + } DRV_LOG(DEBUG, "DEVx flex parser %p created, samples num: %u", (const void *)fp, fp->num_samples); return &fp->entry; -- 2.27.0