From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E13624287D; Fri, 31 Mar 2023 04:24:51 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0051542C54; Fri, 31 Mar 2023 04:24:42 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 3E94D4282D for ; Fri, 31 Mar 2023 04:24:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680229481; x=1711765481; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=cBwWlJKELDQZMZUpZzeT1vHVeLAaXFy8bC4c+RzBkGE=; b=Un0XIRXi7cTmPyu7drWFNf7oiEzQP3pgr/xwDse8cDraDDlnioehDvJk CI3xq9zGP0DcdgkR8ZwzVyt/Qi5qztvHnAsWJBPJCyyLsV+XwbF5MJ277 rQA1BwChPcZo0k2Clc8BAK8v3rj/AO78T76Nu4s34t+y0ZOuctGbeeWKn kukF2gGb+O7bY9goNBr0PnomOQtZB0N970MR+3ojRpk4O5RvSlicpJOHR 9E12Ke4ggXqtf7enHiHCwr1WIx2pl4SETPaP8AOs+WvQaS77ma+BtWy5p cVdlks2sCbheAzsB+nIh4848uj/WqKfUXHxk1x4KMiuWkMNAekCudrq5l g==; X-IronPort-AV: E=McAfee;i="6600,9927,10665"; a="406339268" X-IronPort-AV: E=Sophos;i="5.98,306,1673942400"; d="scan'208";a="406339268" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2023 19:24:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10665"; a="678419756" X-IronPort-AV: E=Sophos;i="5.98,306,1673942400"; d="scan'208";a="678419756" Received: from unknown (HELO npg-dpdk-simeisu-cvl-119d218.sh.intel.com) ([10.67.119.208]) by orsmga007.jf.intel.com with ESMTP; 30 Mar 2023 19:24:38 -0700 From: Simei Su To: thomas@monjalon.net, ferruh.yigit@amd.com, andrew.rybchenko@oktetlabs.ru, kirill.rybalchenko@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, Simei Su Subject: [RFC 2/4] net/ice: add frequency adjustment support for PTP Date: Fri, 31 Mar 2023 10:22:56 +0800 Message-Id: <20230331022258.382085-3-simei.su@intel.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20230331022258.382085-1-simei.su@intel.com> References: <20230331022258.382085-1-simei.su@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add ice support for new ethdev API to adjust frequency for IEEE1588 PTP. Also, this patch reworks code for converting software update to hardware update. Signed-off-by: Simei Su --- drivers/net/ice/ice_ethdev.c | 111 ++++++++++++++++++++++++++++--------------- 1 file changed, 72 insertions(+), 39 deletions(-) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 9a88cf9..fa4d840 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -158,6 +158,7 @@ static int ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev, static int ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev, struct timespec *timestamp); static int ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); +static int ice_timesync_adjust_freq(struct rte_eth_dev *dev, int64_t ppm); static int ice_timesync_read_time(struct rte_eth_dev *dev, struct timespec *timestamp); static int ice_timesync_write_time(struct rte_eth_dev *dev, @@ -274,6 +275,7 @@ static const struct eth_dev_ops ice_eth_dev_ops = { .timesync_read_rx_timestamp = ice_timesync_read_rx_timestamp, .timesync_read_tx_timestamp = ice_timesync_read_tx_timestamp, .timesync_adjust_time = ice_timesync_adjust_time, + .timesync_adjust_freq = ice_timesync_adjust_freq, .timesync_read_time = ice_timesync_read_time, .timesync_write_time = ice_timesync_write_time, .timesync_disable = ice_timesync_disable, @@ -5840,23 +5842,6 @@ ice_timesync_enable(struct rte_eth_dev *dev) } } - /* Initialize cycle counters for system time/RX/TX timestamp */ - memset(&ad->systime_tc, 0, sizeof(struct rte_timecounter)); - memset(&ad->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); - memset(&ad->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); - - ad->systime_tc.cc_mask = ICE_CYCLECOUNTER_MASK; - ad->systime_tc.cc_shift = 0; - ad->systime_tc.nsec_mask = 0; - - ad->rx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK; - ad->rx_tstamp_tc.cc_shift = 0; - ad->rx_tstamp_tc.nsec_mask = 0; - - ad->tx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK; - ad->tx_tstamp_tc.cc_shift = 0; - ad->tx_tstamp_tc.nsec_mask = 0; - ad->ptp_ena = 1; return 0; @@ -5871,14 +5856,13 @@ ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev, ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); struct ice_rx_queue *rxq; uint32_t ts_high; - uint64_t ts_ns, ns; + uint64_t ts_ns; rxq = dev->data->rx_queues[flags]; ts_high = rxq->time_high; ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, ts_high); - ns = rte_timecounter_update(&ad->rx_tstamp_tc, ts_ns); - *timestamp = rte_ns_to_timespec(ns); + *timestamp = rte_ns_to_timespec(ts_ns); return 0; } @@ -5891,7 +5875,7 @@ ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev, struct ice_adapter *ad = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); uint8_t lport; - uint64_t ts_ns, ns, tstamp; + uint64_t ts_ns, tstamp; const uint64_t mask = 0xFFFFFFFF; int ret; @@ -5904,8 +5888,7 @@ ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev, } ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, (tstamp >> 8) & mask); - ns = rte_timecounter_update(&ad->tx_tstamp_tc, ts_ns); - *timestamp = rte_ns_to_timespec(ns); + *timestamp = rte_ns_to_timespec(ts_ns); return 0; } @@ -5913,12 +5896,66 @@ ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev, static int ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) { - struct ice_adapter *ad = - ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint8_t tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc; + uint32_t lo, lo2, hi; + uint64_t time, ns; + int ret; + + if (delta > INT32_MAX || delta < INT32_MIN) { + lo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); + hi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); + lo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); + + if (lo2 < lo) { + lo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); + hi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); + } + + time = ((uint64_t)hi << 32) | lo; + ns = time + delta; + + return ice_ptp_init_time(hw, ns); + } + + ret = ice_ptp_adj_clock(hw, delta, true); + if (ret) + return -1; + + return 0; +} - ad->systime_tc.nsec += delta; - ad->rx_tstamp_tc.nsec += delta; - ad->tx_tstamp_tc.nsec += delta; +#define DEFAULT_INCVAL_E810 0x13b13b13bULL +static int +ice_timesync_adjust_freq(struct rte_eth_dev *dev, int64_t ppm) +{ + uint64_t freq, divisor = 1000000ULL; + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + int64_t incval = DEFAULT_INCVAL_E810, diff; + int neg_adj = 0; + int ret; + + if (ppm < 0) { + neg_adj = 1; + ppm = -ppm; + } + + while ((uint64_t)ppm > UINT64_MAX / incval) { + ppm >>= 2; + divisor >>= 2; + } + + freq = (incval * (uint64_t)ppm) >> 16; + diff = freq / divisor; + + if (neg_adj) + incval -= diff; + else + incval += diff; + + ret = ice_ptp_write_incval_locked(hw, incval); + if (ret) + return -1; return 0; } @@ -5926,15 +5963,14 @@ ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) static int ice_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) { - struct ice_adapter *ad = - ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); + struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint64_t ns; + int ret; ns = rte_timespec_to_ns(ts); - - ad->systime_tc.nsec = ns; - ad->rx_tstamp_tc.nsec = ns; - ad->tx_tstamp_tc.nsec = ns; + ret = ice_ptp_init_time(hw, ns); + if (ret) + return -1; return 0; } @@ -5943,11 +5979,9 @@ static int ice_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) { struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - struct ice_adapter *ad = - ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); uint8_t tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc; uint32_t hi, lo, lo2; - uint64_t time, ns; + uint64_t time; lo = ICE_READ_REG(hw, GLTSYN_TIME_L(tmr_idx)); hi = ICE_READ_REG(hw, GLTSYN_TIME_H(tmr_idx)); @@ -5959,8 +5993,7 @@ ice_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) } time = ((uint64_t)hi << 32) | lo; - ns = rte_timecounter_update(&ad->systime_tc, time); - *ts = rte_ns_to_timespec(ns); + *ts = rte_ns_to_timespec(time); return 0; } -- 2.9.5