From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 50A4B428CE; Tue, 4 Apr 2023 16:19:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7839842B7E; Tue, 4 Apr 2023 16:19:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C9EA140A7E for ; Tue, 4 Apr 2023 16:19:04 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 334Cv92q019623 for ; Tue, 4 Apr 2023 07:19:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0220; bh=jOZF5il/k+lQyaThO9LVOq8kOb/XOs9D7fUwHHyOOGE=; b=fP/xkvOEsG41VodX7roxeMogggnP3j2hUGjpuMyv+TjSe9jpV14sI7dcoqDrIFqAsjq3 2EjemilFuTC3OY2B0XsGMfM0qO7lt0DajdZJhvAtSleDoXniQd3uv3o/SltQeQSuhCcu 8gE8RgS3UnPJgeJ5nJ4BpbYIOmSYKKerfp1ZoJo+vu5mtbchf5pGnaEg3lqjC33HTU/Z eKhQoeKqltBa2XFxwRPiKmrueAFtCT0ufpWkLdIYlYqtWTBQOQc/iThR1cu+PG1VUJFR g09UY6cSqvsZWW67Kv41M5IYfWQZGAfLAvP6C6El51d1eQE880qP2JTG5FwICH5eUtLu CQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ppm4qw0vx-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 04 Apr 2023 07:19:04 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 4 Apr 2023 07:19:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 4 Apr 2023 07:19:02 -0700 Received: from localhost.marvell.com (unknown [10.106.27.249]) by maili.marvell.com (Postfix) with ESMTP id 6D6585B6933; Tue, 4 Apr 2023 07:19:02 -0700 (PDT) From: Sathesh Edara To: , , , "Radha Mohan Chintakuntla" , Veerasenareddy Burru CC: Subject: [PATCH v1 2/9] net/octeon_ep: support CNX10K series SoC Date: Tue, 4 Apr 2023 07:18:47 -0700 Message-ID: <20230404141855.1025625-3-sedara@marvell.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230404141855.1025625-1-sedara@marvell.com> References: <20230404141855.1025625-1-sedara@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 0Tl8Rscj4x-yXUsBmi20rYq72x7vupt_ X-Proofpoint-GUID: 0Tl8Rscj4x-yXUsBmi20rYq72x7vupt_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-04_06,2023-04-04_04,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds the required functionality in the Octeon endpoint driver to support the following CNX10K series endpoint devices. - CN10KA - CN10KB - CNF10KA - CNF10KB Signed-off-by: Sathesh Edara --- drivers/net/octeon_ep/cnxk_ep_vf.h | 5 ++++- drivers/net/octeon_ep/otx_ep_ethdev.c | 21 +++++++++++++++++---- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/net/octeon_ep/cnxk_ep_vf.h b/drivers/net/octeon_ep/cnxk_ep_vf.h index 7162461dd9..aaa5774552 100644 --- a/drivers/net/octeon_ep/cnxk_ep_vf.h +++ b/drivers/net/octeon_ep/cnxk_ep_vf.h @@ -134,7 +134,10 @@ #define CNXK_EP_R_OUT_CTL_ROR_P (1ULL << 24) #define CNXK_EP_R_OUT_CTL_IMODE (1ULL << 23) -#define PCI_DEVID_CNXK_EP_NET_VF 0xB903 +#define PCI_DEVID_CN10KA_EP_NET_VF 0xB903 +#define PCI_DEVID_CNF10KA_EP_NET_VF 0xBA03 +#define PCI_DEVID_CNF10KB_EP_NET_VF 0xBC03 +#define PCI_DEVID_CN10KB_EP_NET_VF 0xBD03 int cnxk_ep_vf_setup_device(struct otx_ep_device *sdpvf); diff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_ep/otx_ep_ethdev.c index 24f62c3e49..b23d52ff84 100644 --- a/drivers/net/octeon_ep/otx_ep_ethdev.c +++ b/drivers/net/octeon_ep/otx_ep_ethdev.c @@ -111,7 +111,10 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf) ret = otx2_ep_vf_setup_device(otx_epvf); otx_epvf->fn_list.disable_io_queues(otx_epvf); break; - case PCI_DEVID_CNXK_EP_NET_VF: + case PCI_DEVID_CN10KA_EP_NET_VF: + case PCI_DEVID_CN10KB_EP_NET_VF: + case PCI_DEVID_CNF10KA_EP_NET_VF: + case PCI_DEVID_CNF10KB_EP_NET_VF: otx_epvf->chip_id = dev_id; ret = cnxk_ep_vf_setup_device(otx_epvf); otx_epvf->fn_list.disable_io_queues(otx_epvf); @@ -150,7 +153,10 @@ otx_epdev_init(struct otx_ep_device *otx_epvf) otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF || otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF) otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts; - else if (otx_epvf->chip_id == PCI_DEVID_CNXK_EP_NET_VF) + else if (otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF) otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts; ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf); otx_epvf->max_rx_queues = ethdev_queues; @@ -501,7 +507,11 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF || otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF || otx_epvf->chip_id == PCI_DEVID_CNF95N_EP_NET_VF || - otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF) + otx_epvf->chip_id == PCI_DEVID_CNF95O_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CN10KA_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CN10KB_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CNF10KA_EP_NET_VF || + otx_epvf->chip_id == PCI_DEVID_CNF10KB_EP_NET_VF) otx_epvf->pkind = SDP_OTX2_PKIND_FS0; else otx_epvf->pkind = SDP_PKIND; @@ -533,7 +543,10 @@ static const struct rte_pci_id pci_id_otx_ep_map[] = { { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95N_EP_NET_VF) }, { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF95O_EP_NET_VF) }, - { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_EP_NET_VF) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KA_EP_NET_VF) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10KB_EP_NET_VF) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF10KA_EP_NET_VF) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNF10KB_EP_NET_VF) }, { .vendor_id = 0, /* sentinel */ } }; -- 2.31.1