From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 490764291B; Tue, 11 Apr 2023 11:12:07 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 33F2240DFD; Tue, 11 Apr 2023 11:12:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 6375840A8B for ; Tue, 11 Apr 2023 11:12:05 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33B8g53q014916 for ; Tue, 11 Apr 2023 02:12:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Y1hLE5YjSxzj9Hh+jJ301m516oo1oLIPCmNBYns3tV4=; b=AeM56L29lqfZxdj0vTJVa57yyV7L2MeNXOBbvyIdmYUfB8ItiS5fdxd37BYv73S1RWg9 pWCC616RMn+7pPAJOshiga7irrkEzH8yDsr9RvSJAuMYLhdcj6NtHDrnhRKKRVm7p+/K 33czqeJ+yxC1l18dVocNcfQy2mghnzr+FxJAPmJAoc8zV25mDQSObKENzCqmt78i90Sv sg0LLWyLa9Dq8191BCX4//0xYEtzmDvLhUOagP4FxbaDnfW215b0sMo1aYzvLxW2MkZg A7K6Lx0XnRtVmXm5gjIq7R6tO0gbYJAAtqp9jybeZRd6mPSwWuY/Qbxih5+w1vKUrZ8v RQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3purfs94e3-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Apr 2023 02:12:04 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 11 Apr 2023 02:12:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 11 Apr 2023 02:12:02 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C76033F706A; Tue, 11 Apr 2023 02:12:00 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Kumar Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 01/21] common/cnxk: allocate dynamic BPIDs Date: Tue, 11 Apr 2023 14:41:24 +0530 Message-ID: <20230411091144.1087887-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: DgSclimjK56d7J1GN-p8HZ84LtrJMGbn X-Proofpoint-GUID: DgSclimjK56d7J1GN-p8HZ84LtrJMGbn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-11_05,2023-04-06_03,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao New mail box to allocate/free dynamic BPIDs based on NIX type. Added to new mail box APIs to get/set RX channel config with new BPIDs. Signed-off-by: Satha Rao --- Depends-on: series-27659 ("add hwpools and support exchanging mbufs between pools") drivers/common/cnxk/roc_cpt.c | 10 +- drivers/common/cnxk/roc_cpt.h | 3 +- drivers/common/cnxk/roc_features.h | 7 ++ drivers/common/cnxk/roc_mbox.h | 31 ++++- drivers/common/cnxk/roc_nix.h | 21 ++++ drivers/common/cnxk/roc_nix_fc.c | 182 +++++++++++++++++++++++++++++ drivers/common/cnxk/roc_nix_inl.c | 24 ++-- drivers/common/cnxk/roc_nix_priv.h | 1 + drivers/common/cnxk/version.map | 5 + 9 files changed, 266 insertions(+), 18 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index dff2fbf2a4..d235ff51ca 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -311,8 +311,7 @@ roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt, } int -roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1, - uint16_t param2, uint16_t opcode) +roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_inline_ipsec_inb_cfg *cfg) { struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); struct cpt_rx_inline_lf_cfg_msg *req; @@ -328,9 +327,10 @@ roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1, } req->sso_pf_func = idev_sso_pffunc_get(); - req->param1 = param1; - req->param2 = param2; - req->opcode = opcode; + req->param1 = cfg->param1; + req->param2 = cfg->param2; + req->opcode = cfg->opcode; + req->bpid = cfg->bpid; rc = mbox_process(mbox); exit: diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index d3a5683dc8..92a18711dc 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -178,8 +178,7 @@ int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot, int __roc_api roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt, struct roc_cpt_inline_ipsec_inb_cfg *cfg); int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, - uint16_t param1, uint16_t param2, - uint16_t opcode); + struct roc_cpt_inline_ipsec_inb_cfg *cfg); int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt); int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt); void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf); diff --git a/drivers/common/cnxk/roc_features.h b/drivers/common/cnxk/roc_features.h index 252f306a86..c2893faa65 100644 --- a/drivers/common/cnxk/roc_features.h +++ b/drivers/common/cnxk/roc_features.h @@ -40,4 +40,11 @@ roc_feature_nix_has_reass(void) return roc_model_is_cn10ka(); } +static inline bool +roc_feature_nix_has_rxchan_multi_bpid(void) +{ + if (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0()) + return true; + return false; +} #endif diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index af3c10b0b0..3d5746b9b8 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -275,7 +275,12 @@ struct mbox_msghdr { M(NIX_SPI_TO_SA_ADD, 0x8026, nix_spi_to_sa_add, nix_spi_to_sa_add_req, \ nix_spi_to_sa_add_rsp) \ M(NIX_SPI_TO_SA_DELETE, 0x8027, nix_spi_to_sa_delete, \ - nix_spi_to_sa_delete_req, msg_rsp) + nix_spi_to_sa_delete_req, msg_rsp) \ + M(NIX_ALLOC_BPIDS, 0x8028, nix_alloc_bpids, nix_alloc_bpid_req, \ + nix_bpids) \ + M(NIX_FREE_BPIDS, 0x8029, nix_free_bpids, nix_bpids, msg_rsp) \ + M(NIX_RX_CHAN_CFG, 0x802a, nix_rx_chan_cfg, nix_rx_chan_cfg, \ + nix_rx_chan_cfg) /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -1186,6 +1191,30 @@ struct nix_bp_cfg_rsp { uint8_t __io chan_cnt; }; +struct nix_alloc_bpid_req { + struct mbox_msghdr hdr; + uint8_t __io bpid_cnt; + uint8_t __io type; + uint64_t __io rsvd; +}; + +struct nix_bpids { +#define ROC_NIX_MAX_BPID_CNT 8 + struct mbox_msghdr hdr; + uint8_t __io bpid_cnt; + uint16_t __io bpids[ROC_NIX_MAX_BPID_CNT]; + uint64_t __io rsvd; +}; + +struct nix_rx_chan_cfg { + struct mbox_msghdr hdr; + uint8_t __io type; /* Interface type(CGX/CPT/LBK) */ + uint8_t __io read; + uint16_t __io chan; /* RX channel to be configured */ + uint64_t __io val; /* NIX_AF_RX_CHAN_CFG value */ + uint64_t __io rsvd; +}; + /* Global NIX inline IPSec configuration */ struct nix_inline_ipsec_cfg { struct mbox_msghdr hdr; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 0ec98ad630..2737bb9517 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -16,6 +16,17 @@ #define ROC_NIX_SQB_LOWER_THRESH 70U #define ROC_NIX_SQB_SLACK 12U +/* Reserved interface types for BPID allocation */ +#define ROC_NIX_INTF_TYPE_CGX 0 +#define ROC_NIX_INTF_TYPE_LBK 1 +#define ROC_NIX_INTF_TYPE_SDP 2 +#define ROC_NIX_INTF_TYPE_CPT 3 +#define ROC_NIX_INTF_TYPE_RSVD 4 + +/* Application based types for BPID allocation, start from end (255 unused rsvd) */ +#define ROC_NIX_INTF_TYPE_CPT_NIX 254 +#define ROC_NIX_INTF_TYPE_SSO 253 + enum roc_nix_rss_reta_sz { ROC_NIX_RSS_RETA_SZ_64 = 64, ROC_NIX_RSS_RETA_SZ_128 = 128, @@ -837,6 +848,16 @@ enum roc_nix_fc_mode __roc_api roc_nix_fc_mode_get(struct roc_nix *roc_nix); void __roc_api roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, uint8_t force, uint8_t tc); +int __roc_api roc_nix_bpids_alloc(struct roc_nix *roc_nix, uint8_t type, + uint8_t bp_cnt, uint16_t *bpids); +int __roc_api roc_nix_bpids_free(struct roc_nix *roc_nix, uint8_t bp_cnt, + uint16_t *bpids); +int __roc_api roc_nix_rx_chan_cfg_get(struct roc_nix *roc_nix, uint16_t chan, + bool is_cpt, uint64_t *cfg); +int __roc_api roc_nix_rx_chan_cfg_set(struct roc_nix *roc_nix, uint16_t chan, + bool is_cpt, uint64_t val); +int __roc_api roc_nix_chan_bpid_set(struct roc_nix *roc_nix, uint16_t chan, + uint64_t bpid, int ena, bool cpt_chan); /* NPC */ int __roc_api roc_nix_npc_promisc_ena_dis(struct roc_nix *roc_nix, int enable); diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index cec83b31f3..3b726673a6 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -104,6 +104,17 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable) nix->cpt_lbpid = 0; } + /* CPT to NIX BP on all channels */ + if (!roc_feature_nix_has_rxchan_multi_bpid() || !nix->cpt_nixbpid) + goto exit; + + mbox_put(mbox); + for (i = 0; i < nix->rx_chan_cnt; i++) { + rc = roc_nix_chan_bpid_set(roc_nix, i, nix->cpt_nixbpid, enable, false); + if (rc) + break; + } + return rc; exit: mbox_put(mbox); return rc; @@ -599,3 +610,174 @@ roc_nix_chan_count_get(struct roc_nix *roc_nix) return nix->chan_cnt; } + +/* Allocate BPID for requested type + * Returns number of BPIDs allocated + * 0 if no BPIDs available + * -ve value on error + */ +int +roc_nix_bpids_alloc(struct roc_nix *roc_nix, uint8_t type, uint8_t bp_cnt, uint16_t *bpids) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = mbox_get(nix->dev.mbox); + struct nix_alloc_bpid_req *req; + struct nix_bpids *rsp; + int rc = -EINVAL; + + /* Use this api for unreserved interface types */ + if ((type < ROC_NIX_INTF_TYPE_RSVD) || (bp_cnt > ROC_NIX_MAX_BPID_CNT) || !bpids) + goto exit; + + rc = -ENOSPC; + req = mbox_alloc_msg_nix_alloc_bpids(mbox); + if (req == NULL) + goto exit; + req->type = type; + req->bpid_cnt = bp_cnt; + + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + goto exit; + + for (rc = 0; rc < rsp->bpid_cnt; rc++) + bpids[rc] = rsp->bpids[rc]; +exit: + mbox_put(mbox); + return rc; +} + +int +roc_nix_bpids_free(struct roc_nix *roc_nix, uint8_t bp_cnt, uint16_t *bpids) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = mbox_get(nix->dev.mbox); + struct nix_bpids *req; + int rc = -EINVAL; + + /* Use this api for unreserved interface types */ + if ((bp_cnt > ROC_NIX_MAX_BPID_CNT) || !bpids) + goto exit; + + rc = -ENOSPC; + req = mbox_alloc_msg_nix_free_bpids(mbox); + if (req == NULL) + goto exit; + for (rc = 0; rc < bp_cnt; rc++) + req->bpids[rc] = bpids[rc]; + req->bpid_cnt = rc; + + rc = mbox_process(mbox); +exit: + mbox_put(mbox); + return rc; +} + +int +roc_nix_rx_chan_cfg_get(struct roc_nix *roc_nix, uint16_t chan, bool is_cpt, uint64_t *cfg) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = mbox_get(nix->dev.mbox); + struct nix_rx_chan_cfg *req; + struct nix_rx_chan_cfg *rsp; + int rc = -EINVAL; + + req = mbox_alloc_msg_nix_rx_chan_cfg(mbox); + if (req == NULL) + goto exit; + if (is_cpt) + req->type = ROC_NIX_INTF_TYPE_CPT; + req->chan = chan; + req->read = 1; + + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + goto exit; + *cfg = rsp->val; +exit: + mbox_put(mbox); + return rc; +} + +int +roc_nix_rx_chan_cfg_set(struct roc_nix *roc_nix, uint16_t chan, bool is_cpt, uint64_t val) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = mbox_get(nix->dev.mbox); + struct nix_rx_chan_cfg *req; + int rc = -EINVAL; + + req = mbox_alloc_msg_nix_rx_chan_cfg(mbox); + if (req == NULL) + goto exit; + if (is_cpt) + req->type = ROC_NIX_INTF_TYPE_CPT; + req->chan = chan; + req->val = val; + req->read = 0; + + rc = mbox_process(mbox); + if (rc) + goto exit; +exit: + mbox_put(mbox); + return rc; +} + +#define NIX_BPID1_ENA 15 +#define NIX_BPID2_ENA 14 +#define NIX_BPID3_ENA 13 + +#define NIX_BPID1_OFF 20 +#define NIX_BPID2_OFF 32 +#define NIX_BPID3_OFF 44 + +int +roc_nix_chan_bpid_set(struct roc_nix *roc_nix, uint16_t chan, uint64_t bpid, int ena, bool cpt_chan) +{ + uint64_t cfg; + int rc; + + if (!roc_feature_nix_has_rxchan_multi_bpid()) + return -ENOTSUP; + + rc = roc_nix_rx_chan_cfg_get(roc_nix, chan, cpt_chan, &cfg); + if (rc) + return rc; + + if (ena) { + if ((((cfg >> NIX_BPID1_OFF) & GENMASK_ULL(8, 0)) == bpid) || + (((cfg >> NIX_BPID2_OFF) & GENMASK_ULL(8, 0)) == bpid) || + (((cfg >> NIX_BPID3_OFF) & GENMASK_ULL(8, 0)) == bpid)) + return 0; + + if (!(cfg & BIT_ULL(NIX_BPID1_ENA))) { + cfg &= ~GENMASK_ULL(NIX_BPID1_OFF + 8, NIX_BPID1_OFF); + cfg |= (((uint64_t)bpid << NIX_BPID1_OFF) | BIT_ULL(NIX_BPID1_ENA)); + } else if (!(cfg & BIT_ULL(NIX_BPID2_ENA))) { + cfg &= ~GENMASK_ULL(NIX_BPID2_OFF + 8, NIX_BPID2_OFF); + cfg |= (((uint64_t)bpid << NIX_BPID2_OFF) | BIT_ULL(NIX_BPID2_ENA)); + } else if (!(cfg & BIT_ULL(NIX_BPID3_ENA))) { + cfg &= ~GENMASK_ULL(NIX_BPID3_OFF + 8, NIX_BPID3_OFF); + cfg |= (((uint64_t)bpid << NIX_BPID3_OFF) | BIT_ULL(NIX_BPID3_ENA)); + } else { + plt_nix_dbg("Exceed maximum BPIDs"); + return -ENOSPC; + } + } else { + if (((cfg >> NIX_BPID1_OFF) & GENMASK_ULL(8, 0)) == bpid) { + cfg &= ~(GENMASK_ULL(NIX_BPID1_OFF + 8, NIX_BPID1_OFF) | + BIT_ULL(NIX_BPID1_ENA)); + } else if (((cfg >> NIX_BPID2_OFF) & GENMASK_ULL(8, 0)) == bpid) { + cfg &= ~(GENMASK_ULL(NIX_BPID2_OFF + 8, NIX_BPID2_OFF) | + BIT_ULL(NIX_BPID2_ENA)); + } else if (((cfg >> NIX_BPID3_OFF) & GENMASK_ULL(8, 0)) == bpid) { + cfg &= ~(GENMASK_ULL(NIX_BPID3_OFF + 8, NIX_BPID3_OFF) | + BIT_ULL(NIX_BPID3_ENA)); + } else { + plt_nix_dbg("BPID not found"); + return -EINVAL; + } + } + return roc_nix_rx_chan_cfg_set(roc_nix, chan, cpt_chan, cfg); +} diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 076d83e8d5..9485bba099 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -603,11 +603,10 @@ int roc_nix_inl_inb_init(struct roc_nix *roc_nix) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct roc_cpt_inline_ipsec_inb_cfg cfg; struct idev_cfg *idev = idev_get_cfg(); + uint16_t bpids[ROC_NIX_MAX_BPID_CNT]; struct roc_cpt *roc_cpt; - uint16_t opcode; - uint16_t param1; - uint16_t param2; int rc; if (idev == NULL) @@ -624,9 +623,9 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) } if (roc_model_is_cn9k()) { - param1 = (ROC_ONF_IPSEC_INB_MAX_L2_SZ >> 3) & 0xf; - param2 = ROC_IE_ON_INB_IKEV2_SINGLE_SA_SUPPORT; - opcode = + cfg.param1 = (ROC_ONF_IPSEC_INB_MAX_L2_SZ >> 3) & 0xf; + cfg.param2 = ROC_IE_ON_INB_IKEV2_SINGLE_SA_SUPPORT; + cfg.opcode = ((ROC_IE_ON_INB_MAX_CTX_LEN << 8) | (ROC_IE_ON_MAJOR_OP_PROCESS_INBOUND_IPSEC | (1 << 6))); } else { @@ -634,13 +633,18 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) u.u16 = 0; u.s.esp_trailer_disable = 1; - param1 = u.u16; - param2 = 0; - opcode = (ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC | (1 << 6)); + cfg.param1 = u.u16; + cfg.param2 = 0; + cfg.opcode = (ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC | (1 << 6)); + rc = roc_nix_bpids_alloc(roc_nix, ROC_NIX_INTF_TYPE_CPT_NIX, 1, bpids); + if (rc > 0) { + nix->cpt_nixbpid = bpids[0]; + cfg.bpid = nix->cpt_nixbpid; + } } /* Do onetime Inbound Inline config in CPTPF */ - rc = roc_cpt_inline_ipsec_inb_cfg(roc_cpt, param1, param2, opcode); + rc = roc_cpt_inline_ipsec_inb_cfg(roc_cpt, &cfg); if (rc && rc != -EEXIST) { plt_err("Failed to setup inbound lf, rc=%d", rc); return rc; diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 2fe9093324..99e27cdc56 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -208,6 +208,7 @@ struct nix { uint16_t outb_se_ring_cnt; uint16_t outb_se_ring_base; uint16_t cpt_lbpid; + uint16_t cpt_nixbpid; bool need_meta_aura; /* Mode provided by driver */ bool inb_inl_dev; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 5281c71550..e7c6f6bce5 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -147,6 +147,9 @@ INTERNAL { roc_nix_bpf_stats_reset; roc_nix_bpf_stats_to_idx; roc_nix_bpf_timeunit_get; + roc_nix_bpids_alloc; + roc_nix_bpids_free; + roc_nix_chan_bpid_set; roc_nix_chan_count_get; roc_nix_cq_dump; roc_nix_cq_fini; @@ -277,6 +280,8 @@ INTERNAL { roc_nix_rss_key_set; roc_nix_rss_reta_get; roc_nix_rss_reta_set; + roc_nix_rx_chan_cfg_get; + roc_nix_rx_chan_cfg_set; roc_nix_rx_drop_re_set; roc_nix_rx_queue_intr_disable; roc_nix_rx_queue_intr_enable; -- 2.25.1