From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0767B4291B; Tue, 11 Apr 2023 11:13:03 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 88E9F42D2C; Tue, 11 Apr 2023 11:12:30 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9992342D16 for ; Tue, 11 Apr 2023 11:12:29 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33B8S2oh021558 for ; Tue, 11 Apr 2023 02:12:28 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=2TkopDAp1mbYKV1nFdILeFSWEfW64qN75y0HbHuESA0=; b=HDTDv8+GrdhwzCC8S38fAEWRAmOmEhgXCQaO1zecnPgNbl98AQgEbNWAre3NE8rYIm45 qpEZ0ySNzrdGEaAdcBCfx3GSu/NibCqNlRisF4VPgVukOwrWUvYB2RhOsqFjkP/pdyp2 TqgE7/MA5G7eVH5s1OzK4jFTsiRE1xDPYzgqhhn0Qr242AVELsfx8+5tBkE623WzMKRF AlZEM1f2FUKYPsnShy62XgREfefkToOxyneqCE0/0auOdFMX2ku90butzlePo6R4klLo TA6VIj+ZLAbWBBNrco/5kv2IEjvY+bhCwj3tnIC/qHMJqkXqMf2VDvkH8yeZ7Zr3fsut LQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3pvt73b1tw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 11 Apr 2023 02:12:28 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 11 Apr 2023 02:12:26 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 11 Apr 2023 02:12:26 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id BD9D23F706A; Tue, 11 Apr 2023 02:12:24 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Kumar Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 09/21] common/cnxk: fetch eng caps for inl outb inst format Date: Tue, 11 Apr 2023 14:41:32 +0530 Message-ID: <20230411091144.1087887-9-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411091144.1087887-1-ndabilpuram@marvell.com> References: <20230411091144.1087887-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: IXYhjsQ4Ob0_q8RS1yrfXThXTxv6hBSf X-Proofpoint-ORIG-GUID: IXYhjsQ4Ob0_q8RS1yrfXThXTxv6hBSf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-11_05,2023-04-06_03,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fetch engine caps and use it along with model check to determine inline outbound instruction format with NIX Tx offset or address. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_cpt.h | 3 + drivers/common/cnxk/roc_nix_inl.c | 101 ++++++++++++++++++++++++++++ drivers/common/cnxk/roc_nix_inl.h | 1 + drivers/common/cnxk/roc_nix_priv.h | 1 + drivers/common/cnxk/version.map | 1 + drivers/net/cnxk/cn10k_ethdev_sec.c | 3 +- drivers/net/cnxk/cnxk_ethdev.c | 2 + drivers/net/cnxk/cnxk_ethdev.h | 3 + 8 files changed, 114 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 92a18711dc..910bd37a0c 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -12,6 +12,9 @@ #define ROC_AE_CPT_BLOCK_TYPE1 0 #define ROC_AE_CPT_BLOCK_TYPE2 1 +#define ROC_LOADFVC_MAJOR_OP 0x01UL +#define ROC_LOADFVC_MINOR_OP 0x08UL + /* Default engine groups */ #define ROC_CPT_DFLT_ENG_GRP_SE 0UL #define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 8592e1cb0b..67f8ce9aa0 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -602,6 +602,96 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable) return rc; } +static void +nix_inl_eng_caps_get(struct nix *nix) +{ + struct roc_cpt_lf *lf = nix->cpt_lf_base; + uintptr_t lmt_base = lf->lmt_base; + union cpt_res_s res, *hw_res; + struct cpt_inst_s inst; + uint64_t *rptr; + + hw_res = plt_zmalloc(sizeof(*hw_res), ROC_CPT_RES_ALIGN); + if (hw_res == NULL) { + plt_err("Couldn't allocate memory for result address"); + return; + } + + rptr = plt_zmalloc(ROC_ALIGN, 0); + if (rptr == NULL) { + plt_err("Couldn't allocate memory for rptr"); + plt_free(hw_res); + return; + } + + /* Fill CPT_INST_S for LOAD_FVC/HW_CRYPTO_SUPPORT microcode op */ + memset(&inst, 0, sizeof(struct cpt_inst_s)); + inst.res_addr = (uint64_t)hw_res; + inst.rptr = (uint64_t)rptr; + inst.w4.s.opcode_major = ROC_LOADFVC_MAJOR_OP; + inst.w4.s.opcode_minor = ROC_LOADFVC_MINOR_OP; + inst.w7.s.egrp = ROC_CPT_DFLT_ENG_GRP_SE; + + /* Use 1 min timeout for the poll */ + const uint64_t timeout = plt_tsc_cycles() + 60 * plt_tsc_hz(); + + if (roc_model_is_cn9k()) { + uint64_t lmt_status; + + hw_res->cn9k.compcode = CPT_COMP_NOT_DONE; + plt_io_wmb(); + + do { + roc_lmt_mov_seg((void *)lmt_base, &inst, 4); + lmt_status = roc_lmt_submit_ldeor(lf->io_addr); + } while (lmt_status != 0); + + /* Wait until CPT instruction completes */ + do { + res.u64[0] = __atomic_load_n(&hw_res->u64[0], __ATOMIC_RELAXED); + if (unlikely(plt_tsc_cycles() > timeout)) + break; + } while (res.cn9k.compcode == CPT_COMP_NOT_DONE); + + if (res.cn9k.compcode != CPT_COMP_GOOD) { + plt_err("LOAD FVC operation timed out"); + return; + } + } else { + uint64_t lmt_arg, io_addr; + uint16_t lmt_id; + + hw_res->cn10k.compcode = CPT_COMP_NOT_DONE; + + /* Use this lcore's LMT line as no one else is using it */ + ROC_LMT_BASE_ID_GET(lmt_base, lmt_id); + memcpy((void *)lmt_base, &inst, sizeof(inst)); + + lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id; + io_addr = lf->io_addr | ROC_CN10K_CPT_INST_DW_M1 << 4; + + roc_lmt_submit_steorl(lmt_arg, io_addr); + plt_io_wmb(); + + /* Wait until CPT instruction completes */ + do { + res.u64[0] = __atomic_load_n(&hw_res->u64[0], __ATOMIC_RELAXED); + if (unlikely(plt_tsc_cycles() > timeout)) + break; + } while (res.cn10k.compcode == CPT_COMP_NOT_DONE); + + if (res.cn10k.compcode != CPT_COMP_GOOD || res.cn10k.uc_compcode) { + plt_err("LOAD FVC operation timed out"); + goto exit; + } + } + + nix->cpt_eng_caps = plt_be_to_cpu_64(*rptr); +exit: + plt_free(rptr); + plt_free(hw_res); +} + int roc_nix_inl_inb_init(struct roc_nix *roc_nix) { @@ -652,6 +742,7 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) plt_err("Failed to setup inbound lf, rc=%d", rc); return rc; } + nix->cpt_eng_caps = roc_cpt->hw_caps[CPT_ENG_TYPE_SE].u; /* Setup Inbound SA table */ rc = nix_inl_inb_sa_tbl_setup(roc_nix); @@ -871,6 +962,8 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix) } } + /* Fetch engine capabilities */ + nix_inl_eng_caps_get(nix); return 0; lf_fini: @@ -1571,3 +1664,11 @@ roc_nix_inl_meta_pool_cb_register(roc_nix_inl_meta_pool_cb_t cb) { meta_pool_cb = cb; } + +uint64_t +roc_nix_inl_eng_caps_get(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + + return nix->cpt_eng_caps; +} diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 6220ba6773..daa21a941a 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -212,5 +212,6 @@ int __roc_api roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb, int __roc_api roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, bool inb, uint16_t sa_len); void __roc_api roc_nix_inl_outb_cpt_lfs_dump(struct roc_nix *roc_nix, FILE *file); +uint64_t __roc_api roc_nix_inl_eng_caps_get(struct roc_nix *roc_nix); #endif /* _ROC_NIX_INL_H_ */ diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index f900a81d8a..6872630dc8 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -209,6 +209,7 @@ struct nix { uint16_t outb_se_ring_base; uint16_t cpt_lbpid; uint16_t cpt_nixbpid; + uint64_t cpt_eng_caps; bool need_meta_aura; /* Mode provided by driver */ bool inb_inl_dev; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index d740d9df81..809fd81b20 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -186,6 +186,7 @@ INTERNAL { roc_nix_inl_dev_rq_put; roc_nix_inl_dev_unlock; roc_nix_inl_dev_xaq_realloc; + roc_nix_inl_eng_caps_get; roc_nix_inl_inb_is_enabled; roc_nix_inl_inb_init; roc_nix_inl_inb_sa_base_get; diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 3c32de0f94..9625704ec1 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -809,7 +809,8 @@ cn10k_eth_sec_session_create(void *device, sess_priv.chksum = (!ipsec->options.ip_csum_enable << 1 | !ipsec->options.l4_csum_enable); sess_priv.dec_ttl = ipsec->options.dec_ttl; - if (roc_feature_nix_has_inl_ipsec_mseg()) + if (roc_feature_nix_has_inl_ipsec_mseg() && + dev->outb.cpt_eng_caps & BIT_ULL(35)) sess_priv.nixtx_off = 1; /* Pointer from eth_sec -> outb_sa */ diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 3bccc34d79..ff0c3b8ed1 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -203,6 +203,8 @@ nix_security_setup(struct cnxk_eth_dev *dev) plt_err("Outbound fc sw mem alloc failed"); goto sa_bmap_free; } + + dev->outb.cpt_eng_caps = roc_nix_inl_eng_caps_get(nix); } return 0; diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 62a06e5d03..d76f5486e6 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -285,6 +285,9 @@ struct cnxk_eth_dev_sec_outb { /* Lock to synchronize sa setup/release */ rte_spinlock_t lock; + + /* Engine caps */ + uint64_t cpt_eng_caps; }; struct cnxk_eth_dev { -- 2.25.1