From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 406F342A02; Wed, 26 Apr 2023 12:28:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7922942D2D; Wed, 26 Apr 2023 12:28:00 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 9AE8240DDA; Wed, 26 Apr 2023 12:27:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504877; x=1714040877; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VQXRouaK+IKPG/RNj7a4FchRTe4L3XqOPsszmvYTy6E=; b=QyrnOpqVtC9EQC6sXWCxv29czJgaea2tA1mBYKMmPjEjtRVjuKhECVQR 7Xl+CQwoYlf/VYRsrGNajbSalJL1gkbMo1U/fmI6d5UwnpUYw27snibtV vc+2N3YJoT1EohRUBC0bOpn6BzHfOMGdh1Xo18plF2BAeFGAevMbild3V 7JuMEvR6qwu2f1pU5dO3b0ubDgsAj/0mFQ0FafSvrnJa8u/fLl6+NnBcy MjqPgDFSgETnAJltKfOyaxIfLUt69jENl2DQQklj/rZTB706GQL3ByTeP LPaTyiUas2Wfij0LOw2Y2fsO6I9AaaL/MVoxR+7bug+Iaf8Fl5cUoZwDW A==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391480" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391480" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:27:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552621" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552621" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:27:53 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org, Charles Stoll Subject: [PATCH v3 02/15] common/idpf/base: fix ctlq message send and receive Date: Wed, 26 Apr 2023 06:22:46 -0400 Message-Id: <20230426102259.205992-3-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fixes the ctlq send and receive functions to not cast the cookie field to a u64 before programming. By doing a cast, it can cause endianness issues as LE will swap the lower 32 and higher 32 bits whereas BE will not. By treating this field as two 32 bit values, both BE and LE will place the retval and opcode in the correct location. Since this field is now being treated as two 32 bit values, the cfg.data section must also be split into a data high and data low. Macros to easily pack and read these fields have also been added. Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Charles Stoll Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_controlq.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 3af81e5a64..8e4d3ee54f 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -311,18 +311,14 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq, for (i = 0; i < num_q_msg; i++) { struct idpf_ctlq_msg *msg = &q_msg[i]; - u64 msg_cookie; desc = IDPF_CTLQ_DESC(cq, cq->next_to_use); desc->opcode = CPU_TO_LE16(msg->opcode); desc->pfid_vfid = CPU_TO_LE16(msg->func_id); - msg_cookie = *(u64 *)&msg->cookie; - desc->cookie_high = - CPU_TO_LE32(IDPF_HI_DWORD(msg_cookie)); - desc->cookie_low = - CPU_TO_LE32(IDPF_LO_DWORD(msg_cookie)); + desc->cookie_high = CPU_TO_LE32(msg->cookie.mbx.chnl_opcode); + desc->cookie_low = CPU_TO_LE32(msg->cookie.mbx.chnl_retval); desc->flags = CPU_TO_LE16((msg->host_id & IDPF_HOST_ID_MASK) << IDPF_CTLQ_FLAG_HOST_ID_S); @@ -620,8 +616,6 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg, num_to_clean = *num_q_msg; for (i = 0; i < num_to_clean; i++) { - u64 msg_cookie; - /* Fetch next descriptor and check if marked as done */ desc = IDPF_CTLQ_DESC(cq, ntc); flags = LE16_TO_CPU(desc->flags); @@ -639,10 +633,8 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg, if (flags & IDPF_CTLQ_FLAG_ERR) ret_code = -EBADMSG; - msg_cookie = (u64)LE32_TO_CPU(desc->cookie_high) << 32; - msg_cookie |= (u64)LE32_TO_CPU(desc->cookie_low); - idpf_memcpy(&q_msg[i].cookie, &msg_cookie, sizeof(u64), - IDPF_NONDMA_TO_NONDMA); + q_msg[i].cookie.mbx.chnl_opcode = LE32_TO_CPU(desc->cookie_high); + q_msg[i].cookie.mbx.chnl_retval = LE32_TO_CPU(desc->cookie_low); q_msg[i].opcode = LE16_TO_CPU(desc->opcode); q_msg[i].data_len = LE16_TO_CPU(desc->datalen); -- 2.25.1