[PATCH 0/7] fixes and improvements to CNXK crypto PMD

[PATCH 0/7] fixes and improvements to CNXK crypto PMD

[Tejasree Kondoj]

This series adds SM3, CN10K PDCP CHAIN support and
improvements to CNXK crypto PMD.

Aakash Sasidharan (1):
  crypto/cnxk: add cryptodev reconfiguration support

Anoob Joseph (2):
  crypto/cnxk: increase max segments
  crypto/cnxk: remove redundant assignment

Tejasree Kondoj (3):
  crypto/cnxk: return error for unsupported paths
  crypto/cnxk: add CN10K pdcp chain support
  crypto/cnxk: set local variables to template value

Vidya Sagar Velumuri (1):
  crypto/cnxk: support SM3 hash

 doc/guides/cryptodevs/cnxk.rst                |   1 +
 doc/guides/cryptodevs/features/cn10k.ini      |   1 +
 drivers/common/cnxk/roc_cpt_sg.h              |   4 +-
 drivers/common/cnxk/roc_se.c                  |  61 ++-
 drivers/common/cnxk/roc_se.h                  |   8 +-
 drivers/crypto/cnxk/cnxk_cryptodev.h          |   2 +-
 .../crypto/cnxk/cnxk_cryptodev_capabilities.c |  32 ++
 drivers/crypto/cnxk/cnxk_cryptodev_ops.c      |  55 ++-
 drivers/crypto/cnxk/cnxk_se.h                 | 444 ++++++++++++------
 9 files changed, 424 insertions(+), 184 deletions(-)

-- 
2.25.1

[PATCH 1/7] crypto/cnxk: return error for unsupported paths

[Tejasree Kondoj]

Returning error in control path for unsupported
algorithm combinations.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
 drivers/common/cnxk/roc_se.c             | 12 +++++++++---
 drivers/crypto/cnxk/cnxk_cryptodev_ops.c |  5 +++++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c
index 5a894013a6..aad2b513c7 100644
--- a/drivers/common/cnxk/roc_se.c
+++ b/drivers/common/cnxk/roc_se.c
@@ -329,6 +329,11 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type,
 		if (!key_len)
 			return -1;
 
+		if (se_ctx->fc_type == ROC_SE_FC_GEN) {
+			plt_err("Cipher and Auth algorithm combination is not supported");
+			return -1;
+		}
+
 		if (roc_model_is_cn9k()) {
 			ci_key = zs_ctx->zuc.onk_ctx.ci_key;
 			zuc_const = zs_ctx->zuc.onk_ctx.zuc_const;
@@ -454,12 +459,13 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type,
 		return 0;
 	}
 
-	if (!se_ctx->fc_type ||
-	    (type && type != ROC_SE_GMAC_TYPE && !se_ctx->enc_cipher))
+	if (!se_ctx->fc_type || (type && type != ROC_SE_GMAC_TYPE && !se_ctx->enc_cipher))
 		se_ctx->fc_type = ROC_SE_HASH_HMAC;
 
-	if (se_ctx->fc_type == ROC_SE_FC_GEN && key_len > 64)
+	if (se_ctx->fc_type == ROC_SE_FC_GEN && key_len > 64) {
+		plt_err("Maximum auth key length supported is 64");
 		return -1;
+	}
 
 	/* For GMAC auth, cipher must be NULL */
 	if (type == ROC_SE_GMAC_TYPE) {
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
index 86efe75cc3..0f59a6c99c 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
@@ -551,6 +551,11 @@ cnxk_sess_fill(struct roc_cpt *roc_cpt, struct rte_crypto_sym_xform *xform,
 		return -EINVAL;
 	}
 
+	if (c_xfrm->cipher.algo == RTE_CRYPTO_CIPHER_AES_XTS) {
+		plt_err("AES XTS with auth algorithm is not supported");
+		return -ENOTSUP;
+	}
+
 	if (c_xfrm->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&
 	    a_xfrm->auth.algo == RTE_CRYPTO_AUTH_SHA1) {
 		plt_dp_err("3DES-CBC + SHA1 is not supported");
-- 
2.25.1

[PATCH 2/7] crypto/cnxk: add cryptodev reconfiguration support

[Tejasree Kondoj]

From: Aakash Sasidharan <asasidharan@marvell.com>

Add support for reconfiguration of cryptodev on cnxk platforms.

Signed-off-by: Aakash Sasidharan <asasidharan@marvell.com>
---
 drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 46 +++++++++++++++---------
 1 file changed, 30 insertions(+), 16 deletions(-)

diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
index 0f59a6c99c..85123d8afe 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
@@ -67,15 +67,42 @@ cnxk_cpt_asym_get_mlen(void)
 	return len;
 }
 
+static int
+cnxk_cpt_dev_clear(struct rte_cryptodev *dev)
+{
+	struct cnxk_cpt_vf *vf = dev->data->dev_private;
+	int ret;
+
+	if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
+		roc_ae_fpm_put();
+		roc_ae_ec_grp_put();
+	}
+
+	ret = roc_cpt_int_misc_cb_unregister(cnxk_cpt_int_misc_cb, NULL);
+	if (ret < 0) {
+		plt_err("Could not unregister CPT_MISC_INT cb");
+		return ret;
+	}
+
+	roc_cpt_dev_clear(&vf->cpt);
+
+	return 0;
+}
+
 int
-cnxk_cpt_dev_config(struct rte_cryptodev *dev,
-		    struct rte_cryptodev_config *conf)
+cnxk_cpt_dev_config(struct rte_cryptodev *dev, struct rte_cryptodev_config *conf)
 {
 	struct cnxk_cpt_vf *vf = dev->data->dev_private;
 	struct roc_cpt *roc_cpt = &vf->cpt;
 	uint16_t nb_lf_avail, nb_lf;
 	int ret;
 
+	/* If this is a reconfigure attempt, clear the device and configure again */
+	if (roc_cpt->nb_lf > 0) {
+		cnxk_cpt_dev_clear(dev);
+		roc_cpt->opaque = NULL;
+	}
+
 	dev->feature_flags = cnxk_cpt_default_ff_get() & ~conf->ff_disable;
 
 	nb_lf_avail = roc_cpt->nb_lf_avail;
@@ -151,7 +178,6 @@ cnxk_cpt_dev_stop(struct rte_cryptodev *dev)
 int
 cnxk_cpt_dev_close(struct rte_cryptodev *dev)
 {
-	struct cnxk_cpt_vf *vf = dev->data->dev_private;
 	uint16_t i;
 	int ret;
 
@@ -163,19 +189,7 @@ cnxk_cpt_dev_close(struct rte_cryptodev *dev)
 		}
 	}
 
-	if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
-		roc_ae_fpm_put();
-		roc_ae_ec_grp_put();
-	}
-
-	ret = roc_cpt_int_misc_cb_unregister(cnxk_cpt_int_misc_cb, NULL);
-	if (ret < 0) {
-		plt_err("Could not unregister CPT_MISC_INT cb");
-		return ret;
-	}
-	roc_cpt_dev_clear(&vf->cpt);
-
-	return 0;
+	return cnxk_cpt_dev_clear(dev);
 }
 
 void
-- 
2.25.1

[PATCH 3/7] crypto/cnxk: add CN10K pdcp chain support

[Tejasree Kondoj]

Adding CN10K pdcp chain support.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
 drivers/common/cnxk/roc_se.c             |  49 ++--
 drivers/common/cnxk/roc_se.h             |   7 +-
 drivers/crypto/cnxk/cnxk_cryptodev_ops.c |   2 +-
 drivers/crypto/cnxk/cnxk_se.h            | 332 +++++++++++++++--------
 4 files changed, 257 insertions(+), 133 deletions(-)

diff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c
index aad2b513c7..8a6fd6671a 100644
--- a/drivers/common/cnxk/roc_se.c
+++ b/drivers/common/cnxk/roc_se.c
@@ -52,9 +52,9 @@ cpt_ciph_aes_key_validate(uint16_t key_len)
 }
 
 static inline int
-cpt_ciph_type_set(roc_se_cipher_type type, struct roc_se_ctx *ctx,
-		  uint16_t key_len)
+cpt_ciph_type_set(roc_se_cipher_type type, struct roc_se_ctx *ctx, uint16_t key_len)
 {
+	bool chained_op = ctx->ciph_then_auth || ctx->auth_then_ciph;
 	int fc_type = 0;
 
 	switch (type) {
@@ -90,21 +90,24 @@ cpt_ciph_type_set(roc_se_cipher_type type, struct roc_se_ctx *ctx,
 		fc_type = ROC_SE_FC_GEN;
 		break;
 	case ROC_SE_ZUC_EEA3:
-		if (ctx->hash_type)
+		if (chained_op) {
+			if (unlikely(key_len != 16))
+				return -1;
 			fc_type = ROC_SE_PDCP_CHAIN;
-		else
+		} else {
 			fc_type = ROC_SE_PDCP;
+		}
 		break;
 	case ROC_SE_SNOW3G_UEA2:
 		if (unlikely(key_len != 16))
 			return -1;
-		if (ctx->hash_type)
+		if (chained_op)
 			fc_type = ROC_SE_PDCP_CHAIN;
 		else
 			fc_type = ROC_SE_PDCP;
 		break;
 	case ROC_SE_AES_CTR_EEA2:
-		if (ctx->hash_type)
+		if (chained_op)
 			fc_type = ROC_SE_PDCP_CHAIN;
 		else
 			fc_type = ROC_SE_PDCP;
@@ -427,6 +430,7 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type,
 				se_ctx->fc_type = ROC_SE_PDCP;
 			}
 			se_ctx->pdcp_auth_alg = ROC_SE_PDCP_ALG_TYPE_AES_CMAC;
+			se_ctx->eia2 = 1;
 			se_ctx->zsk_flags = 0x1;
 			break;
 		case ROC_SE_KASUMI_F9_ECB:
@@ -444,14 +448,19 @@ roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type,
 		default:
 			return -1;
 		}
+
+		if ((se_ctx->fc_type == ROC_SE_PDCP_CHAIN) && (mac_len != 4)) {
+			plt_err("Only digest length of 4 is supported with PDCP chain");
+			return -1;
+		}
+
 		se_ctx->mac_len = mac_len;
 		se_ctx->hash_type = type;
 		pdcp_alg = zs_ctx->zuc.otk_ctx.w0.s.alg_type;
-		if (roc_model_is_cn9k())
-			if (chained_op == true)
-				opcode_minor = se_ctx->ciph_then_auth ? 2 : 3;
-			else
-				opcode_minor = ((1 << 7) | (pdcp_alg << 5) | 1);
+		if (chained_op)
+			opcode_minor = se_ctx->ciph_then_auth ? 2 : 3;
+		else if (roc_model_is_cn9k())
+			opcode_minor = ((1 << 7) | (pdcp_alg << 5) | 1);
 		else
 			opcode_minor = ((1 << 4) | 1);
 
@@ -510,7 +519,7 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui
 	struct roc_se_zuc_snow3g_ctx *zs_ctx = &se_ctx->se_ctx.zs_ctx;
 	struct roc_se_context *fctx = &se_ctx->se_ctx.fctx;
 	struct roc_se_zuc_snow3g_chain_ctx *zs_ch_ctx;
-	uint8_t opcode_minor;
+	uint8_t opcode_minor = 0;
 	uint8_t *zuc_const;
 	uint32_t keyx[4];
 	uint8_t *ci_key;
@@ -699,17 +708,14 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui
 
 success:
 	se_ctx->enc_cipher = type;
-	if (se_ctx->fc_type == ROC_SE_PDCP) {
+	if (se_ctx->fc_type == ROC_SE_PDCP_CHAIN) {
+		se_ctx->template_w4.s.opcode_minor = se_ctx->ciph_then_auth ? 2 : 3;
+	} else if (se_ctx->fc_type == ROC_SE_PDCP) {
 		if (roc_model_is_cn9k())
-			if (chained_op == true)
-				opcode_minor = se_ctx->ciph_then_auth ? 2 : 3;
-			else
-				opcode_minor =
-					((1 << 7) | (se_ctx->pdcp_ci_alg << 5) |
-					 (se_ctx->zsk_flags & 0x7));
+			opcode_minor =
+				((1 << 7) | (se_ctx->pdcp_ci_alg << 5) | (se_ctx->zsk_flags & 0x7));
 		else
 			opcode_minor = ((1 << 4));
-
 		se_ctx->template_w4.s.opcode_minor = opcode_minor;
 	}
 	return 0;
@@ -723,6 +729,9 @@ roc_se_ctx_swap(struct roc_se_ctx *se_ctx)
 	if (roc_model_is_cn9k())
 		return;
 
+	if (se_ctx->fc_type == ROC_SE_PDCP_CHAIN)
+		return;
+
 	zs_ctx->zuc.otk_ctx.w0.u64 = htobe64(zs_ctx->zuc.otk_ctx.w0.u64);
 }
 
diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h
index a0c97b26c5..7771f22c66 100644
--- a/drivers/common/cnxk/roc_se.h
+++ b/drivers/common/cnxk/roc_se.h
@@ -230,14 +230,16 @@ struct roc_se_onk_zuc_chain_ctx {
 	} w0;
 	union {
 		struct {
-			uint8_t encr_lfsr_state[64];
-			uint8_t auth_lfsr_state[64];
+			uint8_t encr_lfsr_state[72];
+			uint8_t auth_lfsr_state[72];
 		};
 		struct {
 			uint8_t ci_key[32];
 			uint8_t ci_zuc_const[32];
+			uint8_t rsvd[8];
 			uint8_t auth_key[32];
 			uint8_t auth_zuc_const[32];
+			uint8_t rsvd1[8];
 		};
 	} st;
 };
@@ -297,6 +299,7 @@ struct roc_se_ctx {
 	uint64_t pdcp_auth_alg : 2;
 	uint64_t ciph_then_auth : 1;
 	uint64_t auth_then_ciph : 1;
+	uint64_t eia2 : 1;
 	union cpt_inst_w4 template_w4;
 	/* Below fields are accessed by hardware */
 	struct se_ctx_s {
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
index 85123d8afe..dd35ee1278 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
@@ -493,7 +493,7 @@ cnxk_sess_fill(struct roc_cpt *roc_cpt, struct rte_crypto_sym_xform *xform,
 	bool pdcp_chain_supported = false;
 	bool ciph_then_auth = false;
 
-	if (roc_model_is_cn9k() && (roc_cpt->hw_caps[CPT_ENG_TYPE_SE].pdcp_chain))
+	if (roc_cpt->hw_caps[CPT_ENG_TYPE_SE].pdcp_chain)
 		pdcp_chain_supported = true;
 
 	if (xform == NULL)
diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h
index 69cd343eea..5fd89442d6 100644
--- a/drivers/crypto/cnxk/cnxk_se.h
+++ b/drivers/crypto/cnxk/cnxk_se.h
@@ -808,6 +808,207 @@ cpt_digest_gen_sg_ver2_prep(uint32_t flags, uint64_t d_lens, struct roc_se_fc_pa
 	return 0;
 }
 
+static inline int
+pdcp_chain_sg1_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx,
+		    struct cpt_inst_s *inst, union cpt_inst_w4 w4, int32_t inputlen,
+		    uint8_t hdr_len, uint64_t offset_ctrl, uint32_t req_flags, uint8_t *cipher_iv,
+		    uint8_t *auth_iv, const int pack_iv, const uint8_t pdcp_ci_alg,
+		    const uint8_t pdcp_auth_alg)
+{
+	struct roc_sglist_comp *scatter_comp, *gather_comp;
+	void *m_vaddr = params->meta_buf.vaddr;
+	uint32_t i, g_size_bytes, s_size_bytes;
+	const uint32_t mac_len = 4;
+	uint8_t *iv_d, *in_buffer;
+	uint64_t *offset_vaddr;
+	uint32_t size;
+
+	/* save space for IV */
+	offset_vaddr = m_vaddr;
+
+	m_vaddr = PLT_PTR_ADD(m_vaddr, ROC_SE_OFF_CTRL_LEN + PLT_ALIGN_CEIL(hdr_len, 8));
+
+	w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;
+
+	/* DPTR has SG list */
+	in_buffer = m_vaddr;
+
+	((uint16_t *)in_buffer)[0] = 0;
+	((uint16_t *)in_buffer)[1] = 0;
+
+	gather_comp = PLT_PTR_ADD(m_vaddr, 8);
+
+	/* Input Gather List */
+	i = 0;
+
+	/* Offset control word followed by IV */
+
+	i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr, ROC_SE_OFF_CTRL_LEN + hdr_len);
+
+	*(uint64_t *)offset_vaddr = offset_ctrl;
+
+	/* Cipher IV */
+	iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN);
+	pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv);
+
+	/* Auth IV */
+	iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16);
+	pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv);
+
+	/* input data */
+	size = inputlen - hdr_len;
+	if (size) {
+		i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov, 0, &size, NULL, 0);
+		if (unlikely(size)) {
+			plt_dp_err("Insufficient buffer space, size %d needed", size);
+			return -1;
+		}
+	}
+	((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
+	g_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);
+
+	/*
+	 * Output Scatter List
+	 */
+
+	i = 0;
+	scatter_comp = PLT_PTR_ADD(gather_comp, g_size_bytes);
+
+	if ((hdr_len)) {
+		i = fill_sg_comp(scatter_comp, i, (uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN,
+				 hdr_len);
+	}
+
+	/* Add output data */
+	if (cpt_ctx->ciph_then_auth && (req_flags & ROC_SE_VALID_MAC_BUF))
+		size = inputlen;
+	else
+		/* Output including mac */
+		size = inputlen + mac_len;
+
+	size -= hdr_len;
+
+	if (size) {
+		i = fill_sg_comp_from_iov(scatter_comp, i, params->dst_iov, 0, &size, NULL, 0);
+
+		if (unlikely(size)) {
+			plt_dp_err("Insufficient buffer space, size %d needed", size);
+			return -1;
+		}
+	}
+
+	((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
+	s_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);
+
+	size = g_size_bytes + s_size_bytes + ROC_SG_LIST_HDR_SIZE;
+
+	/* This is DPTR len in case of SG mode */
+	w4.s.dlen = size;
+	inst->w4.u64 = w4.u64;
+
+	inst->dptr = (uint64_t)in_buffer;
+
+	return 0;
+}
+
+static inline int
+pdcp_chain_sg2_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx,
+		    struct cpt_inst_s *inst, union cpt_inst_w4 w4, int32_t inputlen,
+		    uint8_t hdr_len, uint64_t offset_ctrl, uint32_t req_flags, uint8_t *cipher_iv,
+		    uint8_t *auth_iv, const int pack_iv, const uint8_t pdcp_ci_alg,
+		    const uint8_t pdcp_auth_alg)
+{
+	struct roc_sg2list_comp *gather_comp, *scatter_comp;
+	void *m_vaddr = params->meta_buf.vaddr;
+	const uint32_t mac_len = 4;
+	uint32_t i, g_size_bytes;
+	uint64_t *offset_vaddr;
+	union cpt_inst_w5 w5;
+	union cpt_inst_w6 w6;
+	uint8_t *iv_d;
+	uint32_t size;
+
+	/* save space for IV */
+	offset_vaddr = m_vaddr;
+
+	m_vaddr = PLT_PTR_ADD(m_vaddr, ROC_SE_OFF_CTRL_LEN + RTE_ALIGN_CEIL(hdr_len, 8));
+
+	w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;
+	w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;
+
+	/* DPTR has SG list */
+	inst->dptr = PLT_U64_CAST(m_vaddr);
+
+	gather_comp = m_vaddr;
+
+	/* Input Gather List */
+	i = 0;
+
+	/* Offset control word followed by IV */
+	*(uint64_t *)offset_vaddr = offset_ctrl;
+
+	i = fill_sg2_comp(gather_comp, i, (uint64_t)offset_vaddr, ROC_SE_OFF_CTRL_LEN + hdr_len);
+
+	/* Cipher IV */
+	iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN);
+	pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv);
+
+	/* Auth IV */
+	iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16);
+	pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv);
+
+	/* input data */
+	size = inputlen - hdr_len;
+	if (size) {
+		i = fill_sg2_comp_from_iov(gather_comp, i, params->src_iov, 0, &size, NULL, 0);
+		if (unlikely(size)) {
+			plt_dp_err("Insufficient buffer space, size %d needed", size);
+			return -1;
+		}
+	}
+	w5.s.gather_sz = ((i + 2) / 3);
+	w5.s.dptr = (uint64_t)gather_comp;
+	g_size_bytes = ((i + 2) / 3) * sizeof(struct roc_sg2list_comp);
+
+	/*
+	 * Output Scatter List
+	 */
+
+	i = 0;
+	scatter_comp = PLT_PTR_ADD(gather_comp, g_size_bytes);
+
+	if ((hdr_len))
+		i = fill_sg2_comp(scatter_comp, i, (uint64_t)(offset_vaddr) + ROC_SE_OFF_CTRL_LEN,
+				  hdr_len);
+
+	/* Add output data */
+	if (cpt_ctx->ciph_then_auth && (req_flags & ROC_SE_VALID_MAC_BUF))
+		size = inputlen;
+	else
+		/* Output including mac */
+		size = inputlen + mac_len;
+
+	size -= hdr_len;
+
+	if (size) {
+		i = fill_sg2_comp_from_iov(scatter_comp, i, params->dst_iov, 0, &size, NULL, 0);
+
+		if (unlikely(size)) {
+			plt_dp_err("Insufficient buffer space, size %d needed", size);
+			return -1;
+		}
+	}
+
+	w6.s.scatter_sz = ((i + 2) / 3);
+	w6.s.rptr = (uint64_t)scatter_comp;
+
+	inst->w4.u64 = w4.u64;
+	inst->w5.u64 = w5.u64;
+	inst->w6.u64 = w6.u64;
+
+	return 0;
+}
+
 static __rte_always_inline int
 cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 		  struct roc_se_fc_params *fc_params, struct cpt_inst_s *inst,
@@ -1138,7 +1339,8 @@ cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 
 static __rte_always_inline int
 cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
-			struct roc_se_fc_params *params, struct cpt_inst_s *inst)
+			struct roc_se_fc_params *params, struct cpt_inst_s *inst,
+			const bool is_sg_ver2)
 {
 	uint32_t encr_data_len, auth_data_len, aad_len, passthr_len, pad_len, hdr_len;
 	uint32_t encr_offset, auth_offset, iv_offset = 0;
@@ -1146,10 +1348,10 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
 	uint8_t pdcp_ci_alg, pdcp_auth_alg;
 	union cpt_inst_w4 cpt_inst_w4;
 	struct roc_se_ctx *se_ctx;
+	uint64_t *offset_vaddr;
 	const int iv_len = 32;
-	uint32_t mac_len = 0;
+	uint64_t offset_ctrl;
 	uint8_t pack_iv = 0;
-	void *offset_vaddr;
 	int32_t inputlen;
 	void *dm_vaddr;
 	uint8_t *iv_d;
@@ -1166,7 +1368,6 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
 	}
 
 	se_ctx = params->ctx;
-	mac_len = se_ctx->mac_len;
 	pdcp_ci_alg = se_ctx->pdcp_ci_alg;
 	pdcp_auth_alg = se_ctx->pdcp_auth_alg;
 
@@ -1207,6 +1408,9 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
 
 	inputlen += (encr_offset + pad_len);
 
+	offset_ctrl = rte_cpu_to_be_64(((uint64_t)(aad_len) << 16) | ((uint64_t)(iv_offset) << 8) |
+				       ((uint64_t)(passthr_len)));
+
 	if (likely(((req_flags & ROC_SE_SINGLE_BUF_INPLACE)) &&
 		   ((req_flags & ROC_SE_SINGLE_BUF_HEADROOM)))) {
 
@@ -1215,6 +1419,7 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
 		/* Use Direct mode */
 
 		offset_vaddr = PLT_PTR_SUB(dm_vaddr, ROC_SE_OFF_CTRL_LEN + hdr_len);
+		*offset_vaddr = offset_ctrl;
 
 		/* DPTR */
 		inst->dptr = (uint64_t)offset_vaddr;
@@ -1223,118 +1428,25 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
 
 		cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;
 
-		*(uint64_t *)offset_vaddr =
-			rte_cpu_to_be_64(((uint64_t)(aad_len) << 16) |
-					 ((uint64_t)(iv_offset) << 8) | ((uint64_t)(passthr_len)));
-
 		iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN);
 		pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv);
 
 		iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16);
 		pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv);
 
-	} else {
-		struct roc_sglist_comp *scatter_comp, *gather_comp;
-		void *m_vaddr = params->meta_buf.vaddr;
-		uint32_t i, g_size_bytes, s_size_bytes;
-		uint8_t *in_buffer;
-		uint32_t size;
-
-		/* save space for IV */
-		offset_vaddr = m_vaddr;
-
-		m_vaddr = PLT_PTR_ADD(m_vaddr, ROC_SE_OFF_CTRL_LEN + RTE_ALIGN_CEIL(hdr_len, 8));
-
-		cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;
-
-		/* DPTR has SG list */
-		in_buffer = m_vaddr;
-
-		((uint16_t *)in_buffer)[0] = 0;
-		((uint16_t *)in_buffer)[1] = 0;
-
-		gather_comp = (struct roc_sglist_comp *)((uint8_t *)m_vaddr + 8);
-
-		/* Input Gather List */
-		i = 0;
-
-		/* Offset control word followed by iv */
-
-		i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
-				 ROC_SE_OFF_CTRL_LEN + hdr_len);
-
-		*(uint64_t *)offset_vaddr =
-			rte_cpu_to_be_64(((uint64_t)(aad_len) << 16) |
-					 ((uint64_t)(iv_offset) << 8) | ((uint64_t)(passthr_len)));
-
-		iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN);
-		pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv);
-
-		iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16);
-		pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv);
-
-		/* input data */
-		size = inputlen - hdr_len;
-		if (size) {
-			i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov, 0, &size, NULL,
-						  0);
-			if (unlikely(size)) {
-				plt_dp_err("Insufficient buffer space,"
-					   " size %d needed",
-					   size);
-				return -1;
-			}
-		}
-		((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
-		g_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);
-
-		/*
-		 * Output Scatter List
-		 */
-
-		i = 0;
-		scatter_comp = (struct roc_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes);
-
-		if ((hdr_len)) {
-			i = fill_sg_comp(scatter_comp, i,
-					 (uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN, hdr_len);
-		}
+		inst->w4.u64 = cpt_inst_w4.u64;
+		return 0;
 
-		/* Add output data */
-		if (se_ctx->ciph_then_auth && (req_flags & ROC_SE_VALID_MAC_BUF))
-			size = inputlen;
+	} else {
+		if (is_sg_ver2)
+			return pdcp_chain_sg2_prep(params, se_ctx, inst, cpt_inst_w4, inputlen,
+						   hdr_len, offset_ctrl, req_flags, cipher_iv,
+						   auth_iv, pack_iv, pdcp_ci_alg, pdcp_auth_alg);
 		else
-			/* Output including mac */
-			size = inputlen + mac_len;
-
-		size -= hdr_len;
-
-		if (size) {
-			i = fill_sg_comp_from_iov(scatter_comp, i, params->dst_iov, 0, &size, NULL,
-						  0);
-
-			if (unlikely(size)) {
-				plt_dp_err("Insufficient buffer space,"
-					   " size %d needed",
-					   size);
-				return -1;
-			}
-		}
-
-		((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
-		s_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);
-
-		size = g_size_bytes + s_size_bytes + ROC_SG_LIST_HDR_SIZE;
-
-		/* This is DPTR len in case of SG mode */
-		cpt_inst_w4.s.dlen = size;
-
-		inst->dptr = (uint64_t)in_buffer;
+			return pdcp_chain_sg1_prep(params, se_ctx, inst, cpt_inst_w4, inputlen,
+						   hdr_len, offset_ctrl, req_flags, cipher_iv,
+						   auth_iv, pack_iv, pdcp_ci_alg, pdcp_auth_alg);
 	}
-
-	inst->w4.u64 = cpt_inst_w4.u64;
-
-	return 0;
 }
 
 static __rte_always_inline int
@@ -2520,7 +2632,7 @@ fill_pdcp_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,
 static __rte_always_inline int
 fill_pdcp_chain_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,
 		       struct cpt_qp_meta_info *m_info, struct cpt_inflight_req *infl_req,
-		       struct cpt_inst_s *inst)
+		       struct cpt_inst_s *inst, const bool is_sg_ver2)
 {
 	uint32_t ci_data_length, ci_data_offset, a_data_length, a_data_offset;
 	struct rte_crypto_sym_op *sym_op = cop->sym;
@@ -2643,7 +2755,7 @@ fill_pdcp_chain_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess,
 	}
 
 	/* Finally prepare the instruction */
-	ret = cpt_pdcp_chain_alg_prep(flags, d_offs, d_lens, &fc_params, inst);
+	ret = cpt_pdcp_chain_alg_prep(flags, d_offs, d_lens, &fc_params, inst, is_sg_ver2);
 	if (unlikely(ret)) {
 		plt_dp_err("Could not prepare instruction");
 		goto free_mdata_and_exit;
@@ -2879,7 +2991,7 @@ cpt_sym_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, struct cnxk_
 				     is_sg_ver2);
 		break;
 	case CPT_DP_THREAD_TYPE_PDCP_CHAIN:
-		ret = fill_pdcp_chain_params(op, sess, &qp->meta_info, infl_req, inst);
+		ret = fill_pdcp_chain_params(op, sess, &qp->meta_info, infl_req, inst, is_sg_ver2);
 		break;
 	case CPT_DP_THREAD_TYPE_KASUMI:
 		ret = fill_fc_params(op, sess, &qp->meta_info, infl_req, inst, true, false,
-- 
2.25.1

[PATCH 4/7] crypto/cnxk: support SM3 hash

[Tejasree Kondoj]

From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Add support for SM3 hash operations

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
 doc/guides/cryptodevs/cnxk.rst                |  1 +
 doc/guides/cryptodevs/features/cn10k.ini      |  1 +
 drivers/common/cnxk/roc_se.h                  |  1 +
 drivers/crypto/cnxk/cnxk_cryptodev.h          |  2 +-
 .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 32 +++++++++++++++++++
 drivers/crypto/cnxk/cnxk_cryptodev_ops.c      |  2 +-
 drivers/crypto/cnxk/cnxk_se.h                 | 12 ++++++-
 7 files changed, 48 insertions(+), 3 deletions(-)

diff --git a/doc/guides/cryptodevs/cnxk.rst b/doc/guides/cryptodevs/cnxk.rst
index 3c2e38fefd..991bbc2f99 100644
--- a/doc/guides/cryptodevs/cnxk.rst
+++ b/doc/guides/cryptodevs/cnxk.rst
@@ -72,6 +72,7 @@ Hash algorithms:
 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
 * ``RTE_CRYPTO_AUTH_ZUC_EIA3``
 * ``RTE_CRYPTO_AUTH_AES_CMAC``
+* ``RTE_CRYPTO_AUTH_SM3``
 
 AEAD algorithms:
 
diff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini
index 162d1a25ca..f18b7f3d76 100644
--- a/doc/guides/cryptodevs/features/cn10k.ini
+++ b/doc/guides/cryptodevs/features/cn10k.ini
@@ -73,6 +73,7 @@ SHA3_512        = Y
 SHA3_512 HMAC   = Y
 SHAKE_128       = Y
 SHAKE_256       = Y
+SM3             = Y
 
 ;
 ; Supported AEAD algorithms of 'cn10k' crypto driver.
diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h
index 7771f22c66..1495088915 100644
--- a/drivers/common/cnxk/roc_se.h
+++ b/drivers/common/cnxk/roc_se.h
@@ -81,6 +81,7 @@ typedef enum {
 	ROC_SE_SHA2_SHA512 = 6,
 	ROC_SE_GMAC_TYPE = 7,
 	ROC_SE_POLY1305 = 8,
+	ROC_SE_SM3 = 9,
 	ROC_SE_SHA3_SHA224 = 10,
 	ROC_SE_SHA3_SHA256 = 11,
 	ROC_SE_SHA3_SHA384 = 12,
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h
index 32dec70264..ce45f5d01b 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev.h
+++ b/drivers/crypto/cnxk/cnxk_cryptodev.h
@@ -10,7 +10,7 @@
 
 #include "roc_cpt.h"
 
-#define CNXK_CPT_MAX_CAPS	 48
+#define CNXK_CPT_MAX_CAPS	 49
 #define CNXK_SEC_CRYPTO_MAX_CAPS 16
 #define CNXK_SEC_MAX_CAPS	 9
 #define CNXK_AE_EC_ID_MAX	 8
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
index 19956ffa07..0b02cea308 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
@@ -337,6 +337,29 @@ static const struct rte_cryptodev_capabilities caps_sha1_sha2[] = {
 	},
 };
 
+static const struct rte_cryptodev_capabilities caps_sm3[] = {
+	{	/* SM3 */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SM3,
+				.block_size = 64,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 32,
+					.max = 32,
+					.increment = 0
+				},
+			}, }
+		}, }
+	}
+};
+
 static const struct rte_cryptodev_capabilities caps_sha3[] = {
 	{	/* SHA3_224 */
 		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
@@ -1459,6 +1482,12 @@ cn9k_crypto_caps_add(struct rte_cryptodev_capabilities cnxk_caps[], int *cur_pos
 	    cpt_caps_add(cnxk_caps, cur_pos, caps_docsis, RTE_DIM(caps_docsis));
 }
 
+static void
+cn10k_crypto_caps_add(struct rte_cryptodev_capabilities cnxk_caps[], int *cur_pos)
+{
+	cpt_caps_add(cnxk_caps, cur_pos, caps_sm3, RTE_DIM(caps_sm3));
+}
+
 static void
 crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[],
 		     union cpt_eng_caps *hw_caps)
@@ -1477,6 +1506,9 @@ crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[],
 	if (!roc_model_is_cn10k())
 		cn9k_crypto_caps_add(cnxk_caps, &cur_pos);
 
+	if (roc_model_is_cn10k())
+		cn10k_crypto_caps_add(cnxk_caps, &cur_pos);
+
 	cpt_caps_add(cnxk_caps, &cur_pos, caps_null, RTE_DIM(caps_null));
 	cpt_caps_add(cnxk_caps, &cur_pos, caps_end, RTE_DIM(caps_end));
 
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
index dd35ee1278..649b5754c8 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
@@ -662,7 +662,7 @@ cnxk_cpt_inst_w7_get(struct cnxk_se_sess *sess, struct roc_cpt *roc_cpt)
 		inst_w7.s.cptr += 8;
 
 	/* Set the engine group */
-	if (sess->zsk_flag || sess->aes_ctr_eea2 || sess->is_sha3)
+	if (sess->zsk_flag || sess->aes_ctr_eea2 || sess->is_sha3 || sess->is_sm3)
 		inst_w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_SE];
 	else
 		inst_w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE];
diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h
index 5fd89442d6..2c465a5ab9 100644
--- a/drivers/crypto/cnxk/cnxk_se.h
+++ b/drivers/crypto/cnxk/cnxk_se.h
@@ -44,7 +44,8 @@ struct cnxk_se_sess {
 	uint16_t aad_length;
 	uint8_t is_sha3 : 1;
 	uint8_t short_iv : 1;
-	uint8_t rsvd : 6;
+	uint8_t is_sm3 : 1;
+	uint8_t rsvd : 5;
 	uint8_t mac_len;
 	uint8_t iv_length;
 	uint8_t auth_iv_length;
@@ -199,6 +200,9 @@ cpt_mac_len_verify(struct rte_crypto_auth_xform *auth)
 	case RTE_CRYPTO_AUTH_SHAKE_256:
 		ret = (mac_len <= UINT8_MAX) ? 0 : -1;
 		break;
+	case RTE_CRYPTO_AUTH_SM3:
+		ret = (mac_len <= 32) ? 0 : -1;
+		break;
 	case RTE_CRYPTO_AUTH_NULL:
 		ret = 0;
 		break;
@@ -1999,6 +2003,7 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)
 	uint8_t zsk_flag = 0, zs_auth = 0, aes_gcm = 0, is_null = 0, is_sha3 = 0;
 	struct rte_crypto_auth_xform *a_form;
 	roc_se_auth_type auth_type = 0; /* NULL Auth type */
+	uint8_t is_sm3 = 0;
 
 	if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
 		return fill_sess_gmac(xform, sess);
@@ -2109,6 +2114,10 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)
 		auth_type = ROC_SE_AES_CMAC_EIA2;
 		zsk_flag = ROC_SE_ZS_IA;
 		break;
+	case RTE_CRYPTO_AUTH_SM3:
+		auth_type = ROC_SE_SM3;
+		is_sm3 = 1;
+		break;
 	case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
 	case RTE_CRYPTO_AUTH_AES_CBC_MAC:
 		plt_dp_err("Crypto: Unsupported hash algo %u", a_form->algo);
@@ -2136,6 +2145,7 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)
 	sess->mac_len = a_form->digest_length;
 	sess->is_null = is_null;
 	sess->is_sha3 = is_sha3;
+	sess->is_sm3 = is_sm3;
 	if (zsk_flag) {
 		sess->auth_iv_offset = a_form->iv.offset;
 		sess->auth_iv_length = a_form->iv.length;
-- 
2.25.1

[PATCH 5/7] crypto/cnxk: set local variables to template value

[Tejasree Kondoj]

Initializing local variable from the template populated
in control path.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
 drivers/crypto/cnxk/cnxk_se.h | 25 ++++++++++++-------------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h
index 2c465a5ab9..8715493cae 100644
--- a/drivers/crypto/cnxk/cnxk_se.h
+++ b/drivers/crypto/cnxk/cnxk_se.h
@@ -607,8 +607,7 @@ cpt_digest_gen_sg_ver1_prep(uint32_t flags, uint64_t d_lens, struct roc_se_fc_pa
 	key_len = ctx->auth_key_len;
 	data_len = ROC_SE_AUTH_DLEN(d_lens);
 
-	/*GP op header */
-	cpt_inst_w4.s.opcode_minor = 0;
+	cpt_inst_w4.u64 = ctx->template_w4.u64;
 	cpt_inst_w4.s.param2 = ((uint16_t)hash_type << 8) | mac_len;
 	if (ctx->hmac) {
 		cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_HMAC | ROC_DMA_MODE_SG;
@@ -724,8 +723,7 @@ cpt_digest_gen_sg_ver2_prep(uint32_t flags, uint64_t d_lens, struct roc_se_fc_pa
 	key_len = ctx->auth_key_len;
 	data_len = ROC_SE_AUTH_DLEN(d_lens);
 
-	/*GP op header */
-	cpt_inst_w4.s.opcode_minor = 0;
+	cpt_inst_w4.u64 = ctx->template_w4.u64;
 	cpt_inst_w4.s.param2 = ((uint16_t)hash_type << 8) | mac_len;
 	if (ctx->hmac) {
 		cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_HMAC;
@@ -1049,7 +1047,8 @@ cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	cipher_type = se_ctx->enc_cipher;
 	hash_type = se_ctx->hash_type;
 	mac_len = se_ctx->mac_len;
-	op_minor = se_ctx->template_w4.s.opcode_minor;
+	cpt_inst_w4.u64 = se_ctx->template_w4.u64;
+	op_minor = cpt_inst_w4.s.opcode_minor;
 
 	if (unlikely(!(flags & ROC_SE_VALID_IV_BUF))) {
 		iv_len = 0;
@@ -1080,8 +1079,7 @@ cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 
 	/* Encryption */
 	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_FC;
-	cpt_inst_w4.s.opcode_minor = ROC_SE_FC_MINOR_OP_ENCRYPT;
-	cpt_inst_w4.s.opcode_minor |= (uint64_t)op_minor;
+	cpt_inst_w4.s.opcode_minor |= ROC_SE_FC_MINOR_OP_ENCRYPT;
 
 	if (hash_type == ROC_SE_GMAC_TYPE) {
 		encr_offset = 0;
@@ -1112,7 +1110,6 @@ cpt_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	if (op_minor & ROC_SE_FC_MINOR_OP_HMAC_FIRST)
 		outputlen = enc_dlen;
 
-	/* GP op header */
 	cpt_inst_w4.s.param1 = encr_data_len;
 	cpt_inst_w4.s.param2 = auth_data_len;
 
@@ -1219,7 +1216,8 @@ cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
 	se_ctx = fc_params->ctx;
 	hash_type = se_ctx->hash_type;
 	mac_len = se_ctx->mac_len;
-	op_minor = se_ctx->template_w4.s.opcode_minor;
+	cpt_inst_w4.u64 = se_ctx->template_w4.u64;
+	op_minor = cpt_inst_w4.s.opcode_minor;
 
 	if (unlikely(!(flags & ROC_SE_VALID_IV_BUF))) {
 		iv_len = 0;
@@ -1390,8 +1388,8 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
 		return -1;
 	}
 
+	cpt_inst_w4.u64 = se_ctx->template_w4.u64;
 	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_PDCP_CHAIN;
-	cpt_inst_w4.s.opcode_minor = se_ctx->template_w4.s.opcode_minor;
 
 	cpt_inst_w4.s.param1 = auth_data_len;
 	cpt_inst_w4.s.param2 = 0;
@@ -1475,8 +1473,8 @@ cpt_pdcp_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
 	flags = se_ctx->zsk_flags;
 	mac_len = se_ctx->mac_len;
 
+	cpt_inst_w4.u64 = se_ctx->template_w4.u64;
 	cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_PDCP;
-	cpt_inst_w4.s.opcode_minor = se_ctx->template_w4.s.opcode_minor;
 
 	if (flags == 0x1) {
 		iv_s = params->auth_iv_buf;
@@ -1563,7 +1561,7 @@ cpt_pdcp_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
 	}
 
 	/*
-	 * GP op header, lengths are expected in bits.
+	 * Lengths are expected in bits.
 	 */
 	cpt_inst_w4.s.param1 = encr_data_len;
 	cpt_inst_w4.s.param2 = auth_data_len;
@@ -1637,6 +1635,7 @@ cpt_kasumi_enc_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
 	mac_len = se_ctx->mac_len;
 
 	dir = iv_s[8] & 0x1;
+	cpt_inst_w4.u64 = se_ctx->template_w4.u64;
 
 	if (flags == 0x0) {
 		/* Consider IV len */
@@ -1712,7 +1711,7 @@ cpt_kasumi_dec_prep(uint64_t d_offs, uint64_t d_lens, struct roc_se_fc_params *p
 		((1 << 6) | (se_ctx->k_ecb << 5) | (dir << 4) | (0 << 3) | (flags & 0x7));
 
 	/*
-	 * GP op header, lengths are expected in bits.
+	 * Lengths are expected in bits.
 	 */
 	cpt_inst_w4.s.param1 = encr_data_len;
 
-- 
2.25.1

[PATCH 6/7] crypto/cnxk: increase max segments

[Tejasree Kondoj]

From: Anoob Joseph <anoobj@marvell.com>

Increase max segments to allow max values supported by
hardware/microcode. For SG_VER2, max number of descriptors supported
would be 45. For SG_VER1, maximum number of total components would be
100.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
 drivers/common/cnxk/roc_cpt_sg.h |  4 +-
 drivers/crypto/cnxk/cnxk_se.h    | 90 ++++++++++++++++++++++++--------
 2 files changed, 72 insertions(+), 22 deletions(-)

diff --git a/drivers/common/cnxk/roc_cpt_sg.h b/drivers/common/cnxk/roc_cpt_sg.h
index 8a97e1aa5b..c12187144f 100644
--- a/drivers/common/cnxk/roc_cpt_sg.h
+++ b/drivers/common/cnxk/roc_cpt_sg.h
@@ -7,11 +7,13 @@
 
 #define ROC_DMA_MODE_SG (1 << 7)
 
-#define ROC_MAX_SG_IN_OUT_CNT 32
+#define ROC_MAX_SG_IN_OUT_CNT 128
 #define ROC_MAX_SG_CNT	      (ROC_MAX_SG_IN_OUT_CNT / 2)
 
 #define ROC_SG_LIST_HDR_SIZE (8u)
 #define ROC_SG_ENTRY_SIZE    sizeof(struct roc_sglist_comp)
+#define ROC_SG_MAX_COMP	     25
+#define ROC_SG_MAX_DLEN_SIZE (ROC_SG_LIST_HDR_SIZE + (ROC_SG_MAX_COMP * ROC_SG_ENTRY_SIZE))
 
 struct roc_sglist_comp {
 	union {
diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h
index 8715493cae..784b914137 100644
--- a/drivers/crypto/cnxk/cnxk_se.h
+++ b/drivers/crypto/cnxk/cnxk_se.h
@@ -225,10 +225,10 @@ sg_inst_prep(struct roc_se_fc_params *params, struct cpt_inst_s *inst, uint64_t
 	uint32_t mac_len = 0, aad_len = 0;
 	struct roc_se_ctx *se_ctx;
 	uint32_t i, g_size_bytes;
+	int zsk_flags, ret = 0;
 	uint64_t *offset_vaddr;
 	uint32_t s_size_bytes;
 	uint8_t *in_buffer;
-	int zsk_flags;
 	uint32_t size;
 	uint8_t *iv_d;
 
@@ -395,8 +395,13 @@ sg_inst_prep(struct roc_se_fc_params *params, struct cpt_inst_s *inst, uint64_t
 	/* This is DPTR len in case of SG mode */
 	inst->w4.s.dlen = size;
 
+	if (unlikely(size > ROC_SG_MAX_DLEN_SIZE)) {
+		plt_dp_err("Exceeds max supported components. Reduce segments");
+		ret = -1;
+	}
+
 	inst->dptr = (uint64_t)in_buffer;
-	return 0;
+	return ret;
 }
 
 static __rte_always_inline int
@@ -409,12 +414,13 @@ sg2_inst_prep(struct roc_se_fc_params *params, struct cpt_inst_s *inst, uint64_t
 	void *m_vaddr = params->meta_buf.vaddr;
 	struct roc_se_buf_ptr *aad_buf = NULL;
 	uint32_t mac_len = 0, aad_len = 0;
+	uint16_t scatter_sz, gather_sz;
 	union cpt_inst_w5 cpt_inst_w5;
 	union cpt_inst_w6 cpt_inst_w6;
 	struct roc_se_ctx *se_ctx;
 	uint32_t i, g_size_bytes;
 	uint64_t *offset_vaddr;
-	int zsk_flags;
+	int zsk_flags, ret = 0;
 	uint32_t size;
 	uint8_t *iv_d;
 
@@ -435,6 +441,9 @@ sg2_inst_prep(struct roc_se_fc_params *params, struct cpt_inst_s *inst, uint64_t
 
 	inst->w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;
 
+	/* This is DPTR len in case of SG mode */
+	inst->w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;
+
 	/* iv offset is 0 */
 	*offset_vaddr = offset_ctrl;
 
@@ -505,9 +514,9 @@ sg2_inst_prep(struct roc_se_fc_params *params, struct cpt_inst_s *inst, uint64_t
 		}
 	}
 
-	cpt_inst_w5.s.gather_sz = ((i + 2) / 3);
+	gather_sz = (i + 2) / 3;
+	g_size_bytes = gather_sz * sizeof(struct roc_sg2list_comp);
 
-	g_size_bytes = ((i + 2) / 3) * sizeof(struct roc_sg2list_comp);
 	/*
 	 * Output Scatter List
 	 */
@@ -573,17 +582,23 @@ sg2_inst_prep(struct roc_se_fc_params *params, struct cpt_inst_s *inst, uint64_t
 		}
 	}
 
-	cpt_inst_w6.s.scatter_sz = ((i + 2) / 3);
+	scatter_sz = (i + 2) / 3;
 
-	/* This is DPTR len in case of SG mode */
-	inst->w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;
+	cpt_inst_w5.s.gather_sz = gather_sz;
+	cpt_inst_w6.s.scatter_sz = scatter_sz;
 
 	cpt_inst_w5.s.dptr = (uint64_t)gather_comp;
 	cpt_inst_w6.s.rptr = (uint64_t)scatter_comp;
 
 	inst->w5.u64 = cpt_inst_w5.u64;
 	inst->w6.u64 = cpt_inst_w6.u64;
-	return 0;
+
+	if (unlikely((scatter_sz >> 4) || (gather_sz >> 4))) {
+		plt_dp_err("Exceeds max supported components. Reduce segments");
+		ret = -1;
+	}
+
+	return ret;
 }
 
 static __rte_always_inline int
@@ -599,6 +614,7 @@ cpt_digest_gen_sg_ver1_prep(uint32_t flags, uint64_t d_lens, struct roc_se_fc_pa
 	struct roc_se_ctx *ctx;
 	uint8_t *in_buffer;
 	uint32_t size, i;
+	int ret = 0;
 
 	ctx = params->ctx;
 
@@ -692,22 +708,27 @@ cpt_digest_gen_sg_ver1_prep(uint32_t flags, uint64_t d_lens, struct roc_se_fc_pa
 
 	size = g_size_bytes + s_size_bytes + ROC_SG_LIST_HDR_SIZE;
 
+	if (unlikely(size > ROC_SG_MAX_DLEN_SIZE)) {
+		plt_dp_err("Exceeds max supported components. Reduce segments");
+		ret = -1;
+	}
+
 	/* This is DPTR len in case of SG mode */
 	cpt_inst_w4.s.dlen = size;
 
 	inst->dptr = (uint64_t)in_buffer;
 	inst->w4.u64 = cpt_inst_w4.u64;
 
-	return 0;
+	return ret;
 }
 
 static __rte_always_inline int
 cpt_digest_gen_sg_ver2_prep(uint32_t flags, uint64_t d_lens, struct roc_se_fc_params *params,
 			    struct cpt_inst_s *inst)
 {
+	uint16_t data_len, mac_len, key_len, scatter_sz, gather_sz;
 	struct roc_sg2list_comp *gather_comp, *scatter_comp;
 	void *m_vaddr = params->meta_buf.vaddr;
-	uint16_t data_len, mac_len, key_len;
 	union cpt_inst_w4 cpt_inst_w4;
 	union cpt_inst_w5 cpt_inst_w5;
 	union cpt_inst_w6 cpt_inst_w6;
@@ -715,6 +736,7 @@ cpt_digest_gen_sg_ver2_prep(uint32_t flags, uint64_t d_lens, struct roc_se_fc_pa
 	struct roc_se_ctx *ctx;
 	uint32_t g_size_bytes;
 	uint32_t size, i;
+	int ret = 0;
 
 	ctx = params->ctx;
 
@@ -768,9 +790,9 @@ cpt_digest_gen_sg_ver2_prep(uint32_t flags, uint64_t d_lens, struct roc_se_fc_pa
 		plt_dp_err("Insufficient dst IOV size, short by %dB", size);
 		return -1;
 	}
-	cpt_inst_w5.s.gather_sz = ((i + 2) / 3);
 
-	g_size_bytes = ((i + 2) / 3) * sizeof(struct roc_sg2list_comp);
+	gather_sz = (i + 2) / 3;
+	g_size_bytes = gather_sz * sizeof(struct roc_sg2list_comp);
 
 	/*
 	 * Output Gather list
@@ -797,7 +819,10 @@ cpt_digest_gen_sg_ver2_prep(uint32_t flags, uint64_t d_lens, struct roc_se_fc_pa
 		}
 	}
 
-	cpt_inst_w6.s.scatter_sz = ((i + 2) / 3);
+	scatter_sz = (i + 2) / 3;
+
+	cpt_inst_w5.s.gather_sz = gather_sz;
+	cpt_inst_w6.s.scatter_sz = scatter_sz;
 
 	cpt_inst_w5.s.dptr = (uint64_t)gather_comp;
 	cpt_inst_w6.s.rptr = (uint64_t)scatter_comp;
@@ -807,7 +832,12 @@ cpt_digest_gen_sg_ver2_prep(uint32_t flags, uint64_t d_lens, struct roc_se_fc_pa
 
 	inst->w4.u64 = cpt_inst_w4.u64;
 
-	return 0;
+	if (unlikely((scatter_sz >> 4) || (gather_sz >> 4))) {
+		plt_dp_err("Exceeds max supported components. Reduce segments");
+		ret = -1;
+	}
+
+	return ret;
 }
 
 static inline int
@@ -824,6 +854,7 @@ pdcp_chain_sg1_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx,
 	uint8_t *iv_d, *in_buffer;
 	uint64_t *offset_vaddr;
 	uint32_t size;
+	int ret = 0;
 
 	/* save space for IV */
 	offset_vaddr = m_vaddr;
@@ -904,13 +935,18 @@ pdcp_chain_sg1_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx,
 
 	size = g_size_bytes + s_size_bytes + ROC_SG_LIST_HDR_SIZE;
 
+	if (unlikely(size > ROC_SG_MAX_DLEN_SIZE)) {
+		plt_dp_err("Exceeds max supported components. Reduce segments");
+		ret = -1;
+	}
+
 	/* This is DPTR len in case of SG mode */
 	w4.s.dlen = size;
 	inst->w4.u64 = w4.u64;
 
 	inst->dptr = (uint64_t)in_buffer;
 
-	return 0;
+	return ret;
 }
 
 static inline int
@@ -922,6 +958,7 @@ pdcp_chain_sg2_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx,
 {
 	struct roc_sg2list_comp *gather_comp, *scatter_comp;
 	void *m_vaddr = params->meta_buf.vaddr;
+	uint16_t scatter_sz, gather_sz;
 	const uint32_t mac_len = 4;
 	uint32_t i, g_size_bytes;
 	uint64_t *offset_vaddr;
@@ -929,6 +966,7 @@ pdcp_chain_sg2_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx,
 	union cpt_inst_w6 w6;
 	uint8_t *iv_d;
 	uint32_t size;
+	int ret = 0;
 
 	/* save space for IV */
 	offset_vaddr = m_vaddr;
@@ -968,9 +1006,9 @@ pdcp_chain_sg2_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx,
 			return -1;
 		}
 	}
-	w5.s.gather_sz = ((i + 2) / 3);
-	w5.s.dptr = (uint64_t)gather_comp;
-	g_size_bytes = ((i + 2) / 3) * sizeof(struct roc_sg2list_comp);
+
+	gather_sz = (i + 2) / 3;
+	g_size_bytes = gather_sz * sizeof(struct roc_sg2list_comp);
 
 	/*
 	 * Output Scatter List
@@ -1001,14 +1039,24 @@ pdcp_chain_sg2_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx,
 		}
 	}
 
-	w6.s.scatter_sz = ((i + 2) / 3);
+	scatter_sz = (i + 2) / 3;
+
+	w5.s.gather_sz = gather_sz;
+	w6.s.scatter_sz = scatter_sz;
+
+	w5.s.dptr = (uint64_t)gather_comp;
 	w6.s.rptr = (uint64_t)scatter_comp;
 
 	inst->w4.u64 = w4.u64;
 	inst->w5.u64 = w5.u64;
 	inst->w6.u64 = w6.u64;
 
-	return 0;
+	if (unlikely((scatter_sz >> 4) || (gather_sz >> 4))) {
+		plt_dp_err("Exceeds max supported components. Reduce segments");
+		ret = -1;
+	}
+
+	return ret;
 }
 
 static __rte_always_inline int
-- 
2.25.1

[PATCH 7/7] crypto/cnxk: remove redundant assignment

[Tejasree Kondoj]

From: Anoob Joseph <anoobj@marvell.com>

In SG_VER2, DPTR would be poining at gather_comp. No need to set it
m_vaddr only to be overwritten.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
 drivers/crypto/cnxk/cnxk_se.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h
index 784b914137..3a12af3594 100644
--- a/drivers/crypto/cnxk/cnxk_se.h
+++ b/drivers/crypto/cnxk/cnxk_se.h
@@ -976,9 +976,6 @@ pdcp_chain_sg2_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx,
 	w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;
 	w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;
 
-	/* DPTR has SG list */
-	inst->dptr = PLT_U64_CAST(m_vaddr);
-
 	gather_comp = m_vaddr;
 
 	/* Input Gather List */
-- 
2.25.1

RE: [PATCH 0/7] fixes and improvements to CNXK crypto PMD

[Akhil Goyal]

> Subject: [PATCH 0/7] fixes and improvements to CNXK crypto PMD
> 
> This series adds SM3, CN10K PDCP CHAIN support and
> improvements to CNXK crypto PMD.
> 
> Aakash Sasidharan (1):
>   crypto/cnxk: add cryptodev reconfiguration support
> 
> Anoob Joseph (2):
>   crypto/cnxk: increase max segments
>   crypto/cnxk: remove redundant assignment
> 
> Tejasree Kondoj (3):
>   crypto/cnxk: return error for unsupported paths
>   crypto/cnxk: add CN10K pdcp chain support
>   crypto/cnxk: set local variables to template value
> 
> Vidya Sagar Velumuri (1):
>   crypto/cnxk: support SM3 hash
> 
>  doc/guides/cryptodevs/cnxk.rst                |   1 +
>  doc/guides/cryptodevs/features/cn10k.ini      |   1 +
>  drivers/common/cnxk/roc_cpt_sg.h              |   4 +-
>  drivers/common/cnxk/roc_se.c                  |  61 ++-
>  drivers/common/cnxk/roc_se.h                  |   8 +-
>  drivers/crypto/cnxk/cnxk_cryptodev.h          |   2 +-
>  .../crypto/cnxk/cnxk_cryptodev_capabilities.c |  32 ++
>  drivers/crypto/cnxk/cnxk_cryptodev_ops.c      |  55 ++-
>  drivers/crypto/cnxk/cnxk_se.h                 | 444 ++++++++++++------
>  9 files changed, 424 insertions(+), 184 deletions(-)

Applied to dpdk-next-crypto
Updated release notes for SM3 and PDCP chain support