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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT087.mail.protection.outlook.com (10.13.177.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6411.30 via Frontend Transport; Wed, 24 May 2023 10:08:49 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Wed, 24 May 2023 03:08:38 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 24 May 2023 03:08:36 -0700 From: Dong Zhou To: , , , "Matan Azrad" CC: , Subject: [PATCH v2 3/3] net/mlx5/hws: add support for infiniband BTH match Date: Wed, 24 May 2023 13:08:05 +0300 Message-ID: <20230524100805.2215154-4-dongzhou@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230524100805.2215154-1-dongzhou@nvidia.com> References: <20230511075504.664871-1-dongzhou@nvidia.com> <20230524100805.2215154-1-dongzhou@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT087:EE_|SA1PR12MB8988:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e73761f-9ba9-492a-fefe-08db5c3edeb0 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2023 10:08:49.5051 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e73761f-9ba9-492a-fefe-08db5c3edeb0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT087.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8988 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds support to match opcode and dst_qp fields in infiniband BTH. Currently, only the RoCEv2 packet is supported, the input BTH match item is defaulted to match one RoCEv2 packet. Signed-off-by: Dong Zhou --- drivers/net/mlx5/hws/mlx5dr_definer.c | 76 ++++++++++++++++++++++++++- drivers/net/mlx5/hws/mlx5dr_definer.h | 2 + drivers/net/mlx5/mlx5_flow_hw.c | 1 + 3 files changed, 78 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index f92d3e8e1f..1a427c9b64 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -10,6 +10,7 @@ #define ETH_TYPE_IPV6_VXLAN 0x86DD #define ETH_VXLAN_DEFAULT_PORT 4789 #define IP_UDP_PORT_MPLS 6635 +#define UDP_ROCEV2_PORT 4791 #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS) #define STE_NO_VLAN 0x0 @@ -171,7 +172,9 @@ struct mlx5dr_definer_conv_data { X(SET_BE16, gre_opt_checksum, v->checksum_rsvd.checksum, rte_flow_item_gre_opt) \ X(SET, meter_color, rte_col_2_mlx5_col(v->color), rte_flow_item_meter_color) \ X(SET_BE32, ipsec_spi, v->hdr.spi, rte_flow_item_esp) \ - X(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp) + X(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp) \ + X(SET, ib_l4_udp_port, UDP_ROCEV2_PORT, rte_flow_item_ib_bth) \ + X(SET, ib_l4_opcode, v->hdr.opcode, rte_flow_item_ib_bth) /* Item set function format */ #define X(set_type, func_name, value, item_type) \ @@ -583,6 +586,16 @@ mlx5dr_definer_mpls_label_set(struct mlx5dr_definer_fc *fc, memcpy(tag + fc->byte_off + sizeof(v->label_tc_s), &v->ttl, sizeof(v->ttl)); } +static void +mlx5dr_definer_ib_l4_qp_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + const struct rte_flow_item_ib_bth *v = item_spec; + + memcpy(tag + fc->byte_off, &v->hdr.dst_qp, sizeof(v->hdr.dst_qp)); +} + static int mlx5dr_definer_conv_item_eth(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, @@ -2041,6 +2054,63 @@ mlx5dr_definer_conv_item_flex_parser(struct mlx5dr_definer_conv_data *cd, return 0; } +static int +mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_ib_bth *m = item->mask; + struct mlx5dr_definer_fc *fc; + bool inner = cd->tunnel; + + /* In order to match on RoCEv2(layer4 ib), we must match + * on ip_protocol and l4_dport. + */ + if (!cd->relaxed) { + fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; + if (!fc->tag_set) { + fc->item_idx = item_idx; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->tag_set = &mlx5dr_definer_udp_protocol_set; + DR_CALC_SET(fc, eth_l2, l4_type_bwc, inner); + } + + fc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)]; + if (!fc->tag_set) { + fc->item_idx = item_idx; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->tag_set = &mlx5dr_definer_ib_l4_udp_port_set; + DR_CALC_SET(fc, eth_l4, destination_port, inner); + } + } + + if (!m) + return 0; + + if (m->hdr.se || m->hdr.m || m->hdr.padcnt || m->hdr.tver || + m->hdr.pkey || m->hdr.f || m->hdr.b || m->hdr.rsvd0 || + m->hdr.a || m->hdr.rsvd1 || !is_mem_zero(m->hdr.psn, 3)) { + rte_errno = ENOTSUP; + return rte_errno; + } + + if (m->hdr.opcode) { + fc = &cd->fc[MLX5DR_DEFINER_FNAME_IB_L4_OPCODE]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ib_l4_opcode_set; + DR_CALC_SET_HDR(fc, ib_l4, opcode); + } + + if (!is_mem_zero(m->hdr.dst_qp, 3)) { + fc = &cd->fc[MLX5DR_DEFINER_FNAME_IB_L4_QPN]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ib_l4_qp_set; + DR_CALC_SET_HDR(fc, ib_l4, qp); + } + + return 0; +} + static int mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, struct mlx5dr_match_template *mt, @@ -2182,6 +2252,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, item_flags |= MLX5_FLOW_LAYER_MPLS; cd.mpls_idx++; break; + case RTE_FLOW_ITEM_TYPE_IB_BTH: + ret = mlx5dr_definer_conv_item_ib_l4(&cd, items, i); + item_flags |= MLX5_FLOW_ITEM_IB_BTH; + break; default: DR_LOG(ERR, "Unsupported item type %d", items->type); rte_errno = ENOTSUP; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 90ec4ce845..6b645f4cf0 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -134,6 +134,8 @@ enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_OKS2_MPLS2_I, MLX5DR_DEFINER_FNAME_OKS2_MPLS3_I, MLX5DR_DEFINER_FNAME_OKS2_MPLS4_I, + MLX5DR_DEFINER_FNAME_IB_L4_OPCODE, + MLX5DR_DEFINER_FNAME_IB_L4_QPN, MLX5DR_DEFINER_FNAME_MAX, }; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 853c94af9c..f9e7f844ea 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -4969,6 +4969,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: case RTE_FLOW_ITEM_TYPE_ESP: case RTE_FLOW_ITEM_TYPE_FLEX: + case RTE_FLOW_ITEM_TYPE_IB_BTH: break; case RTE_FLOW_ITEM_TYPE_INTEGRITY: /* -- 2.27.0