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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by CO1NAM11FT114.mail.protection.outlook.com (10.13.174.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6411.30 via Frontend Transport; Thu, 25 May 2023 10:08:32 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 25 May 2023 05:08:32 -0500 Received: from xhdipdslab41.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 25 May 2023 05:08:29 -0500 From: Nipun Gupta To: , , , , , CC: , , , Nipun Gupta Subject: [PATCH v5 0/5] Support AMD CDX bus Date: Thu, 25 May 2023 15:38:16 +0530 Message-ID: <20230525100821.12148-1-nipun.gupta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230124140746.594066-1-nipun.gupta@amd.com> References: <20230124140746.594066-1-nipun.gupta@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT114:EE_|DS0PR12MB6605:EE_ X-MS-Office365-Filtering-Correlation-Id: 4106dc3b-436c-4b29-4894-08db5d07ff3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230028)(4636009)(346002)(396003)(39860400002)(376002)(136003)(451199021)(36840700001)(40470700004)(46966006)(5660300002)(54906003)(110136005)(478600001)(966005)(8676002)(41300700001)(1076003)(44832011)(6666004)(316002)(70586007)(4326008)(26005)(70206006)(8936002)(186003)(83380400001)(47076005)(40460700003)(2616005)(2906002)(336012)(426003)(36860700001)(82740400003)(81166007)(356005)(40480700001)(82310400005)(86362001)(36756003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2023 10:08:32.9789 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4106dc3b-436c-4b29-4894-08db5d07ff3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT114.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6605 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The CDX devices are memory mapped on system bus for embedded CPUs. It uses sysfs interface and the vfio-cdx driver to discover and initialize the CDX devices. The CDX bus and VFIO support is available at Xilinx/AMD open source tree: https://github.com/Xilinx/linux-xlnx (drivers/cdx/ and drivers/vfio/cdx) Linux AMD CDX bus patches has been added into linux tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/cdx VFIO patches are also submitted in upstream: https://www.spinics.net/lists/kvm/msg310623.html CDX is a Hardware Architecture designed for AMD FPGA devices. It consists of mechanism for interaction between FPGA, Firmware and the APUs (Application CPUs). Firmware resides on RPU (Realtime CPUs) which interacts with the FPGA program manager and the APUs. The RPU provides memory-mapped interface (RPU if) which is used to communicate with APUs. VFIO CDX driver provides the CDX device resources like MMIO and interrupts to map to user-space. DPDK CDX bus uses sysfs interface and the vfio-cdx driver to discover and initialize the CDX devices for user-space applications. Changes v4->v5 - Split patch and have a separate commit for eal interrupt field (irq_count) and corresponding set/get APIs (rte_intr_irq_count_set, rte_intr_irq_count_get) - Renamed "CDX bus" to "AMD CDX bus" in documentation/commit headings - Removed unnecessary headers Changes v3->v4: - removed platform specific patch (adding config for ARM CDX) from this series Changes v2->v3: - merged cdx bus compilation enablement in the first patch - fixed issue reported by check-git-log.sh - updated release notes - updated offset to uint64_t instead of off_t in cdx_map_resource Changes v1->v2: - Moved file rte_cdx_bus.h to internal bus_cdx_driver.h and added this file to deivce_cdx_headers - Moved cdx.h to private.h - Removed rte_ prefix from the static symbols in .c files. Changes RFC->v1: - Marked few API's as internal which were not required to be provided to user. Nipun Gupta (5): bus/cdx: introduce AMD CDX bus bus/cdx: add DMA map and unmap support eal/interrupts: add IRQ count in interrupt handle bus/cdx: add support for MSI bus/cdx: support plug unplug and dev iterator MAINTAINERS | 5 + doc/guides/rel_notes/release_23_07.rst | 6 + drivers/bus/cdx/bus_cdx_driver.h | 222 ++++++++ drivers/bus/cdx/cdx.c | 690 +++++++++++++++++++++++++ drivers/bus/cdx/cdx_logs.h | 37 ++ drivers/bus/cdx/cdx_vfio.c | 605 ++++++++++++++++++++++ drivers/bus/cdx/meson.build | 13 + drivers/bus/cdx/private.h | 46 ++ drivers/bus/cdx/version.map | 13 + drivers/bus/meson.build | 1 + lib/eal/common/eal_common_interrupts.c | 21 + lib/eal/common/eal_interrupts.h | 1 + lib/eal/include/rte_interrupts.h | 32 ++ lib/eal/version.map | 2 + 14 files changed, 1694 insertions(+) create mode 100644 drivers/bus/cdx/bus_cdx_driver.h create mode 100644 drivers/bus/cdx/cdx.c create mode 100644 drivers/bus/cdx/cdx_logs.h create mode 100644 drivers/bus/cdx/cdx_vfio.c create mode 100644 drivers/bus/cdx/meson.build create mode 100644 drivers/bus/cdx/private.h create mode 100644 drivers/bus/cdx/version.map -- 2.17.1