From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BF75842C54; Wed, 7 Jun 2023 23:00:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8F95541611; Wed, 7 Jun 2023 23:00:55 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 086C3410D0 for ; Wed, 7 Jun 2023 23:00:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686171654; x=1717707654; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=87zaIHjEIAeUhTdBCHeXphxUn/laeOEhl4FdD9Bsx8M=; b=dLgTlcTaKk3lSBetFOcTPucmJCYuVSn6+9CUYP1KrtDEtNl35W2T4g5O lyIl0dhKX/SuqIoKKGnIqOtN9l62VMZFKUPSMKdWao8Ht2CUzsL/+moxL 7Go0/mEtEe43HAqwGaONEC02Q0RB43lQf7dXPiJ4J2krsF5OHaDEzjACI Hu5adWW26+VJy3DpS3ZSRULcHFRkcTc0xcU7RUyFhQDEW53CCBP6PXjhn mm5L7/VDzd6ECw6VLbqxKLSMAVQaGwPyNjksioXJ9kO3qbFngTvfCHfM3 fBiH2a2aLWFYvuoH5BNj5j7dDfJtid39E6ivz4En4H0wnth6jEaKKQvph Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="360439931" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="360439931" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 14:00:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="660100056" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="660100056" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orsmga003.jf.intel.com with ESMTP; 07 Jun 2023 14:00:52 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, mike.ximing.chen@intel.com, Abdullah Sevincer Subject: [PATCH v1] event/dlb2: add support for disabling PASID Date: Wed, 7 Jun 2023 16:00:50 -0500 Message-Id: <20230607210050.107944-1-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org vfio-pci driver in Linux kernel 6.2 enables PASID by default. In DLB hardware, enabling PASID puts DLB in SIOV mode. This breaks DLB PF-PMD mode. For DLB PF-PMD mode to function properly PASID needs to be disabled for kernel 6.2. In this commit this issue is addressed and PASID is disabled by writing a zero to PASID control register. Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/pf/dlb2_main.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index 717aa4fc08..63868e2388 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -46,6 +46,7 @@ #define DLB2_PCI_CAP_ID_MSIX 0x11 #define DLB2_PCI_EXT_CAP_ID_PRI 0x13 #define DLB2_PCI_EXT_CAP_ID_ACS 0xD +#define DLB2_PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ #define DLB2_PCI_PRI_CTRL_ENABLE 0x1 #define DLB2_PCI_PRI_ALLOC_REQ 0xC @@ -64,6 +65,8 @@ #define DLB2_PCI_ACS_CR 0x8 #define DLB2_PCI_ACS_UF 0x10 #define DLB2_PCI_ACS_EC 0x20 +#define DLB2_PCI_PASID_CTRL 0x06 /* PASID control register */ +#define DLB2_PCI_PASID_CAP_OFFSET 0x148 /* PASID capability offset */ static int dlb2_pci_find_capability(struct rte_pci_device *pdev, uint32_t id) { @@ -257,12 +260,14 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) uint16_t rt_ctl_word; uint32_t pri_reqs_dword; uint16_t pri_ctrl_word; + uint16_t pasid_ctrl; int pcie_cap_offset; int pri_cap_offset; int msix_cap_offset; int err_cap_offset; int acs_cap_offset; + int pasid_cap_offset; int wait_count; uint16_t devsta_busy_word; @@ -582,6 +587,28 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } + /* The current Linux kernel vfio driver does not expose PASID capability to + * users. It also enables PASID by default, which breaks DLB PF PMD. We have + * to use the hardcoded offset for now to disable PASID. + */ + pasid_cap_offset = DLB2_PCI_PASID_CAP_OFFSET; + + off = pasid_cap_offset + DLB2_PCI_PASID_CTRL; + if (rte_pci_read_config(pdev, &pasid_ctrl, 2, off) != 2) + pasid_ctrl = 0; + + if (pasid_ctrl) { + DLB2_INFO(dlb2_dev, "DLB2 disabling pasid...\n"); + + pasid_ctrl = 0; + ret = rte_pci_write_config(pdev, &pasid_ctrl, 2, off); + if (ret != 2) { + DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", + __func__, (int)off); + return ret; + } + } + return 0; } -- 2.25.1