From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5482542CA0; Tue, 13 Jun 2023 09:17:15 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7714542D38; Tue, 13 Jun 2023 09:16:50 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 86A8342D2C for ; Tue, 13 Jun 2023 09:16:49 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35D567pr005545; Tue, 13 Jun 2023 00:16:48 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=bXI/acpXUZVKal/KYoxd95y8N5Gz8oVwqTMZLMqMVBY=; b=KDWAimUcPoz9yr1OmNmPPDR9rsnmMhi3JF6sOrVxugZWeWf62y99M6P8d1mx8tUQU/Qo JdxwV6efQu6x9Alzwu+3xPfP7u5CaOLL1O2DwAlgrdcMS8iqolkORqY0kmJ/ePCVpO9T PMpSnlApC07ymWK6Z5egWUcBx29RKj9ge2JFEMsjKHjrP04Fi+0kq6PA0pSdoH9GXkF4 hA1B7I/iGv4G6hjsK8jgzEcnTIncNnAdrIXCc0nmMACAtdha7aYl0n7ZQdnp5MXMVLiL QCJlh2D+Q8F+25JJOQBmagAEK7dxW5jSYgwiTFillMgeVXVui6nvgY8XsYtf6swtNmpv og== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r650235fw-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 13 Jun 2023 00:16:48 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 13 Jun 2023 00:16:46 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 13 Jun 2023 00:16:46 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id DEE365E6861; Tue, 13 Jun 2023 00:16:43 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v3 05/15] common/cnxk: add MACsec PN and LMAC mode configuration Date: Tue, 13 Jun 2023 12:46:04 +0530 Message-ID: <20230613071614.2259604-6-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613071614.2259604-1-gakhil@marvell.com> References: <20230607152819.226838-1-gakhil@marvell.com> <20230613071614.2259604-1-gakhil@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 5KWWCUC-JHZ44i8J01jqeQRM0teKroPK X-Proofpoint-GUID: 5KWWCUC-JHZ44i8J01jqeQRM0teKroPK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-13_04,2023-06-12_02,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs for setting packet number and LMAC related configurations. Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_mbox.h | 56 +++++++++++++++++++++ drivers/common/cnxk/roc_mcs.c | 71 +++++++++++++++++++++++++++ drivers/common/cnxk/roc_mcs.h | 48 ++++++++++++++++++ drivers/common/cnxk/roc_mcs_sec_cfg.c | 31 ++++++++++++ drivers/common/cnxk/version.map | 5 ++ 5 files changed, 211 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index fcfcc90f6c..62c5c3a3ce 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -308,7 +308,11 @@ struct mbox_msghdr { M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, msg_rsp) \ M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, msg_rsp) \ M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, msg_rsp) \ + M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, msg_rsp) \ + M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, msg_rsp) \ M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ + M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \ + M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, msg_rsp) \ /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -812,6 +816,34 @@ struct mcs_flowid_ena_dis_entry { uint64_t __io rsvd; }; +struct mcs_pn_table_write_req { + struct mbox_msghdr hdr; + uint64_t __io next_pn; + uint8_t __io pn_id; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + +struct mcs_cam_entry_read_req { + struct mbox_msghdr hdr; + uint8_t __io rsrc_type; /* TCAM/SECY/SC/SA/PN */ + uint8_t __io rsrc_id; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + +struct mcs_cam_entry_read_rsp { + struct mbox_msghdr hdr; + uint64_t __io reg_val[10]; + uint8_t __io rsrc_type; + uint8_t __io rsrc_id; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + struct mcs_hw_info { struct mbox_msghdr hdr; uint8_t __io num_mcs_blks; /* Number of MCS blocks */ @@ -822,6 +854,30 @@ struct mcs_hw_info { uint64_t __io rsvd[16]; }; +struct mcs_set_active_lmac { + struct mbox_msghdr hdr; + uint32_t __io lmac_bmap; /* bitmap of active lmac per mcs block */ + uint8_t __io mcs_id; + uint16_t __io channel_base; /* MCS channel base */ + uint64_t __io rsvd; +}; + +struct mcs_set_lmac_mode { + struct mbox_msghdr hdr; + uint8_t __io mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */ + uint8_t __io lmac_id; + uint8_t __io mcs_id; + uint64_t __io rsvd; +}; + +struct mcs_set_pn_threshold { + struct mbox_msghdr hdr; + uint64_t __io threshold; + uint8_t __io xpn; /* '1' for setting xpn threshold */ + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; /* NPA mbox message formats */ diff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c index 20433eae83..38f1e9b2f7 100644 --- a/drivers/common/cnxk/roc_mcs.c +++ b/drivers/common/cnxk/roc_mcs.c @@ -38,6 +38,77 @@ roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info) return rc; } +int +roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lmac) +{ + struct mcs_set_active_lmac *req; + struct msg_rsp *rsp; + + /* Only needed for 105N */ + if (!roc_model_is_cnf10kb()) + return 0; + + if (lmac == NULL) + return -EINVAL; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_set_active_lmac(mcs->mbox); + if (req == NULL) + return -ENOMEM; + + req->lmac_bmap = lmac->lmac_bmap; + req->channel_base = lmac->channel_base; + req->mcs_id = mcs->idx; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port) +{ + struct mcs_set_lmac_mode *req; + struct msg_rsp *rsp; + + if (port == NULL) + return -EINVAL; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_set_lmac_mode(mcs->mbox); + if (req == NULL) + return -ENOMEM; + + req->lmac_id = port->lmac_id; + req->mcs_id = mcs->idx; + req->mode = port->mode; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *pn) +{ + struct mcs_set_pn_threshold *req; + struct msg_rsp *rsp; + + if (pn == NULL) + return -EINVAL; + + MCS_SUPPORT_CHECK; + + req = mbox_alloc_msg_mcs_set_pn_threshold(mcs->mbox); + if (req == NULL) + return -ENOMEM; + + req->threshold = pn->threshold; + req->mcs_id = mcs->idx; + req->dir = pn->dir; + req->xpn = pn->xpn; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + static int mcs_alloc_bmap(uint16_t entries, void **mem, struct plt_bitmap **bmap) { diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index 38c2d5626a..bedae3bf42 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -88,6 +88,25 @@ struct roc_mcs_flowid_ena_dis_entry { uint8_t dir; }; +struct roc_mcs_pn_table_write_req { + uint64_t next_pn; + uint8_t pn_id; + uint8_t dir; +}; + +struct roc_mcs_cam_entry_read_req { + uint8_t rsrc_type; /* TCAM/SECY/SC/SA/PN */ + uint8_t rsrc_id; + uint8_t dir; +}; + +struct roc_mcs_cam_entry_read_rsp { + uint64_t reg_val[10]; + uint8_t rsrc_type; + uint8_t rsrc_id; + uint8_t dir; +}; + struct roc_mcs_hw_info { uint8_t num_mcs_blks; /* Number of MCS blocks */ uint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */ @@ -97,6 +116,24 @@ struct roc_mcs_hw_info { uint64_t rsvd[16]; }; +struct roc_mcs_set_lmac_mode { + uint8_t mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */ + uint8_t lmac_id; + uint64_t rsvd; +}; + +struct roc_mcs_set_active_lmac { + uint32_t lmac_bmap; /* bitmap of active lmac per mcs block */ + uint16_t channel_base; /* MCS channel base */ + uint64_t rsvd; +}; + +struct roc_mcs_set_pn_threshold { + uint64_t threshold; + uint8_t xpn; /* '1' for setting xpn threshold */ + uint8_t dir; + uint64_t rsvd; +}; struct roc_mcs { TAILQ_ENTRY(roc_mcs) next; @@ -119,6 +156,12 @@ __roc_api void roc_mcs_dev_fini(struct roc_mcs *mcs); __roc_api struct roc_mcs *roc_mcs_dev_get(uint8_t mcs_idx); /* HW info get */ __roc_api int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info); +/* Active lmac bmap set */ +__roc_api int roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lmac); +/* Port bypass mode set */ +__roc_api int roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port); +/* (X)PN threshold set */ +__roc_api int roc_mcs_pn_threshold_set(struct roc_mcs *mcs, struct roc_mcs_set_pn_threshold *pn); /* Resource allocation and free */ __roc_api int roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req, @@ -129,6 +172,11 @@ __roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy); __roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy); +/* PN Table read and write */ +__roc_api int roc_mcs_pn_table_write(struct roc_mcs *mcs, + struct roc_mcs_pn_table_write_req *pn_table); +__roc_api int roc_mcs_pn_table_read(struct roc_mcs *mcs, + struct roc_mcs_pn_table_write_req *pn_table); /* RX SC read, write and enable */ __roc_api int roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); diff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c index 44b4919bbc..7b3a4c91e8 100644 --- a/drivers/common/cnxk/roc_mcs_sec_cfg.c +++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c @@ -210,6 +210,37 @@ roc_mcs_sa_policy_read(struct roc_mcs *mcs __plt_unused, return -ENOTSUP; } +int +roc_mcs_pn_table_write(struct roc_mcs *mcs, struct roc_mcs_pn_table_write_req *pn_table) +{ + struct mcs_pn_table_write_req *pn; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (pn_table == NULL) + return -EINVAL; + + pn = mbox_alloc_msg_mcs_pn_table_write(mcs->mbox); + if (pn == NULL) + return -ENOMEM; + + pn->next_pn = pn_table->next_pn; + pn->pn_id = pn_table->pn_id; + pn->mcs_id = mcs->idx; + pn->dir = pn_table->dir; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_pn_table_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_pn_table_write_req *sa __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} int roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam) diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 3d9da3b187..0591747961 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -135,6 +135,7 @@ INTERNAL { roc_se_auth_key_set; roc_se_ciph_key_set; roc_se_ctx_init; + roc_mcs_active_lmac_set; roc_mcs_dev_init; roc_mcs_dev_fini; roc_mcs_dev_get; @@ -142,6 +143,10 @@ INTERNAL { roc_mcs_flowid_entry_read; roc_mcs_flowid_entry_write; roc_mcs_hw_info_get; + roc_mcs_lmac_mode_set; + roc_mcs_pn_table_write; + roc_mcs_pn_table_read; + roc_mcs_pn_threshold_set; roc_mcs_rsrc_alloc; roc_mcs_rsrc_free; roc_mcs_rx_sc_cam_enable; -- 2.25.1