From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2FEB542CB3; Wed, 14 Jun 2023 15:09:51 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6107F42D2C; Wed, 14 Jun 2023 15:09:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id BF1FD427F5 for ; Wed, 14 Jun 2023 15:09:23 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35EC91hg002710; Wed, 14 Jun 2023 06:09:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=bnFD9/OUEzWmPfLm8E8nHv/BF2enJToxVDUWQc9uSa4=; b=ckD3GNd7maA3mQ8k1nVLzgLsZe+fVjxQKL4lpo0RV2WlIOn7FttZ7oOWeDYt8jvRw6Rg MYXfIJGi5TxaAWuG9Vzm1vbNztui10N37hs6MkoUz2haXgHIS9fxE9FMjCTebSrEyhZI s9lOtjbj56IbMumJBgIKbhJCpqb2nDRJDE7ImI5nc0KhEZ/P/z5iNMwgeg+Xs7aB/HEe SNIJFKWxETR/mqT5yTY2pPe6OjB3V+r1lXrjEvGagIble2EkiaEqYwukjQBUw5DJ8Cac ab/x2T63J3RgrlmQ6vedyr2vIu2iGpyKaA0LFYhhJjRyCLffyhUgRJ9tvNeftpqohn6R dg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3r4rpkm4b0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 14 Jun 2023 06:09:23 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 14 Jun 2023 06:09:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 14 Jun 2023 06:09:20 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 9833A3F70B3; Wed, 14 Jun 2023 06:09:17 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v5 04/15] common/cnxk: add MACsec secy and flow configuration Date: Wed, 14 Jun 2023 18:38:50 +0530 Message-ID: <20230614130901.3245809-5-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230614130901.3245809-1-gakhil@marvell.com> References: <20230613102009.2390568-1-gakhil@marvell.com> <20230614130901.3245809-1-gakhil@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: AFn_97NbnALeDc1SMIgealcQzOLgTwiP X-Proofpoint-GUID: AFn_97NbnALeDc1SMIgealcQzOLgTwiP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-14_08,2023-06-14_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs to configure MACsec secy policy and flow entries. Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_mbox.h | 38 +++++++++ drivers/common/cnxk/roc_mcs.h | 37 +++++++++ drivers/common/cnxk/roc_mcs_sec_cfg.c | 115 ++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 5 ++ 4 files changed, 195 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 40b761ee99..fcfcc90f6c 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -300,10 +300,14 @@ struct mbox_msghdr { M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ mcs_alloc_rsrc_rsp) \ M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ + M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \ + msg_rsp) \ + M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, msg_rsp) \ M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, msg_rsp) \ M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, msg_rsp) \ M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, msg_rsp) \ M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, msg_rsp) \ + M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, msg_rsp) \ M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ /* Messages initiated by AF (range 0xC00 - 0xDFF) */ @@ -729,6 +733,31 @@ struct mcs_free_rsrc_req { uint64_t __io rsvd; }; +struct mcs_flowid_entry_write_req { + struct mbox_msghdr hdr; + uint64_t __io data[4]; + uint64_t __io mask[4]; + uint64_t __io sci; /* CNF10K-B for tx_secy_mem_map */ + uint8_t __io flow_id; + uint8_t __io secy_id; /* secyid for which flowid is mapped */ + /* sc_id is Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ + uint8_t __io sc_id; + uint8_t __io ena; /* Enable tcam entry */ + uint8_t __io ctr_pkt; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + +struct mcs_secy_plcy_write_req { + struct mbox_msghdr hdr; + uint64_t __io plcy; + uint8_t __io secy_id; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + /* RX SC_CAM mapping */ struct mcs_rx_sc_cam_write_req { struct mbox_msghdr hdr; @@ -774,6 +803,15 @@ struct mcs_rx_sc_sa_map { uint64_t __io rsvd; }; +struct mcs_flowid_ena_dis_entry { + struct mbox_msghdr hdr; + uint8_t __io flow_id; + uint8_t __io ena; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + struct mcs_hw_info { struct mbox_msghdr hdr; uint8_t __io num_mcs_blks; /* Number of MCS blocks */ diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index 1fb36b5eaa..33bd372ed0 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -32,6 +32,24 @@ struct roc_mcs_free_rsrc_req { uint8_t all; /* Free all the cam resources */ }; +struct roc_mcs_flowid_entry_write_req { + uint64_t data[4]; + uint64_t mask[4]; + uint64_t sci; /* 105N for tx_secy_mem_map */ + uint8_t flow_id; + uint8_t secy_id; /* secyid for which flowid is mapped */ + uint8_t sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */ + uint8_t ena; /* Enable tcam entry */ + uint8_t ctr_pkt; + uint8_t dir; +}; + +struct roc_mcs_secy_plcy_write_req { + uint64_t plcy; + uint8_t secy_id; + uint8_t dir; +}; + /* RX SC_CAM mapping */ struct roc_mcs_rx_sc_cam_write_req { uint64_t sci; /* SCI */ @@ -64,6 +82,12 @@ struct roc_mcs_rx_sc_sa_map { uint8_t an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ }; +struct roc_mcs_flowid_ena_dis_entry { + uint8_t flow_id; + uint8_t ena; + uint8_t dir; +}; + struct roc_mcs_hw_info { uint8_t num_mcs_blks; /* Number of MCS blocks */ uint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */ @@ -113,6 +137,11 @@ __roc_api int roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); __roc_api int roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); +/* SECY policy read and write */ +__roc_api int roc_mcs_secy_policy_write(struct roc_mcs *mcs, + struct roc_mcs_secy_plcy_write_req *secy_plcy); +__roc_api int roc_mcs_secy_policy_read(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); /* RX SC-SA MAP read and write */ __roc_api int roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map); @@ -124,4 +153,12 @@ __roc_api int roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs, __roc_api int roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs, struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map); +/* Flow entry read, write and enable */ +__roc_api int roc_mcs_flowid_entry_write(struct roc_mcs *mcs, + struct roc_mcs_flowid_entry_write_req *flowid_req); +__roc_api int roc_mcs_flowid_entry_read(struct roc_mcs *mcs, + struct roc_mcs_flowid_entry_write_req *flowid_rsp); +__roc_api int roc_mcs_flowid_entry_enable(struct roc_mcs *mcs, + struct roc_mcs_flowid_ena_dis_entry *entry); + #endif /* ROC_MCS_H */ diff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c index 9b87952112..44b4919bbc 100644 --- a/drivers/common/cnxk/roc_mcs_sec_cfg.c +++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c @@ -267,6 +267,38 @@ roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs __plt_unused, return -ENOTSUP; } +int +roc_mcs_secy_policy_write(struct roc_mcs *mcs, struct roc_mcs_secy_plcy_write_req *secy_plcy) +{ + struct mcs_secy_plcy_write_req *secy; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (secy_plcy == NULL) + return -EINVAL; + + secy = mbox_alloc_msg_mcs_secy_plcy_write(mcs->mbox); + if (secy == NULL) + return -ENOMEM; + + secy->plcy = secy_plcy->plcy; + secy->secy_id = secy_plcy->secy_id; + secy->mcs_id = mcs->idx; + secy->dir = secy_plcy->dir; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_secy_policy_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} + int roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map) { @@ -380,3 +412,86 @@ roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused, return -ENOTSUP; } + +int +roc_mcs_flowid_entry_write(struct roc_mcs *mcs, struct roc_mcs_flowid_entry_write_req *flowid_req) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_flowid_entry_write_req *flow_req; + struct msg_rsp *rsp; + uint8_t port; + int rc; + + MCS_SUPPORT_CHECK; + + if (flowid_req == NULL) + return -EINVAL; + + flow_req = mbox_alloc_msg_mcs_flowid_entry_write(mcs->mbox); + if (flow_req == NULL) + return -ENOMEM; + + mbox_memcpy(flow_req->data, flowid_req->data, sizeof(uint64_t) * 4); + mbox_memcpy(flow_req->mask, flowid_req->mask, sizeof(uint64_t) * 4); + flow_req->sci = flowid_req->sci; + flow_req->flow_id = flowid_req->flow_id; + flow_req->secy_id = flowid_req->secy_id; + flow_req->sc_id = flowid_req->sc_id; + flow_req->ena = flowid_req->ena; + flow_req->ctr_pkt = flowid_req->ctr_pkt; + flow_req->mcs_id = mcs->idx; + flow_req->dir = flowid_req->dir; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + if (flow_req->mask[3] & (BIT_ULL(10) | BIT_ULL(11))) + return rc; + + port = (flow_req->data[3] >> 10) & 0x3; + + plt_bitmap_set(priv->port_rsrc[port].tcam_bmap, + flowid_req->flow_id + + ((flowid_req->dir == MCS_TX) ? priv->tcam_entries : 0)); + plt_bitmap_set(priv->port_rsrc[port].secy_bmap, + flowid_req->secy_id + + ((flowid_req->dir == MCS_TX) ? priv->secy_entries : 0)); + + if (flowid_req->dir == MCS_TX) + plt_bitmap_set(priv->port_rsrc[port].sc_bmap, priv->sc_entries + flowid_req->sc_id); + + return 0; +} + +int +roc_mcs_flowid_entry_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_flowid_entry_write_req *flowid_rsp __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} + +int +roc_mcs_flowid_entry_enable(struct roc_mcs *mcs, struct roc_mcs_flowid_ena_dis_entry *entry) +{ + struct mcs_flowid_ena_dis_entry *flow_entry; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (entry == NULL) + return -EINVAL; + + flow_entry = mbox_alloc_msg_mcs_flowid_ena_entry(mcs->mbox); + if (flow_entry == NULL) + return -ENOMEM; + + flow_entry->flow_id = entry->flow_id; + flow_entry->ena = entry->ena; + flow_entry->mcs_id = mcs->idx; + flow_entry->dir = entry->dir; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index dbfda62ad1..3d9da3b187 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -138,6 +138,9 @@ INTERNAL { roc_mcs_dev_init; roc_mcs_dev_fini; roc_mcs_dev_get; + roc_mcs_flowid_entry_enable; + roc_mcs_flowid_entry_read; + roc_mcs_flowid_entry_write; roc_mcs_hw_info_get; roc_mcs_rsrc_alloc; roc_mcs_rsrc_free; @@ -148,6 +151,8 @@ INTERNAL { roc_mcs_rx_sc_sa_map_write; roc_mcs_sa_policy_read; roc_mcs_sa_policy_write; + roc_mcs_secy_policy_read; + roc_mcs_secy_policy_write; roc_mcs_tx_sc_sa_map_read; roc_mcs_tx_sc_sa_map_write; roc_nix_bpf_alloc; -- 2.25.1