From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC65E42D07; Tue, 20 Jun 2023 12:21:38 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0433C42D30; Tue, 20 Jun 2023 12:21:24 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A0C7C42D16 for ; Tue, 20 Jun 2023 12:21:22 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35K9wleK024114 for ; Tue, 20 Jun 2023 03:21:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=D5yrDooSPeeEyhPu5UV7ZZrQjiWUeS5qWoBUuOQeE7I=; b=Qon+dYH8kmrgyIU9UqmCkyJ2pdmutFWihnw5uDZQeVy/m7SFPqeA0adn0yaiJsWGiygm 2EM9Ei6pwTx1AY96eNjSN+JMgt145FYh9jWC8idgx3WK011n2tFE+8XoLG3QNMFRvbre 49CXKNsBd2bQ/QIuK247WoLy8097XiinSge87eSg0D/o06/vBab6RkWdhjYVtwZ9/4cV q+imHQdUf4rcOxqx+/KRCN0NFRvUt2UffE4pb5U2M7Mt3kX3H/+nBvnUk4QXzT1MoVHv SB8dedDNXrceLZhUjU5ixIzaPCGgqUC7025LayQSRiEJxobwZWpLodo4V63/rAsJQf49 3w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3r9cbkfd3s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 20 Jun 2023 03:21:21 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 20 Jun 2023 03:21:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 20 Jun 2023 03:21:20 -0700 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 3A9B23F70D4; Tue, 20 Jun 2023 03:21:16 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Aakash Sasidharan , Gowrishankar Muthukrishnan , Vidya Sagar Velumuri , Subject: [PATCH v3 4/8] crypto/cnxk: enable context cache for 103XX Date: Tue, 20 Jun 2023 15:51:02 +0530 Message-ID: <20230620102106.3970544-5-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230620102106.3970544-1-ktejasree@marvell.com> References: <20230620102106.3970544-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: UT0ge2goLSg96CVMlpmoir6U8K_r5hJm X-Proofpoint-ORIG-GUID: UT0ge2goLSg96CVMlpmoir6U8K_r5hJm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-20_06,2023-06-16_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enabling context cache for SE instructions on 106B0 and 103XX. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 6 +++--- drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 8 ++++++++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 2018b0eba5..d0c99d37e8 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -653,7 +653,7 @@ cnxk_cpt_inst_w7_get(struct cnxk_se_sess *sess, struct roc_cpt *roc_cpt) inst_w7.s.cptr = (uint64_t)&sess->roc_se_ctx.se_ctx; - if (roc_errata_cpt_hang_on_mixed_ctx_val()) + if (hw_ctx_cache_enable()) inst_w7.s.ctx_val = 1; else inst_w7.s.cptr += 8; @@ -729,7 +729,7 @@ sym_session_configure(struct roc_cpt *roc_cpt, struct rte_crypto_sym_xform *xfor sess_priv->cpt_inst_w7 = cnxk_cpt_inst_w7_get(sess_priv, roc_cpt); - if (roc_errata_cpt_hang_on_mixed_ctx_val()) + if (hw_ctx_cache_enable()) roc_se_ctx_init(&sess_priv->roc_se_ctx); return 0; @@ -755,7 +755,7 @@ sym_session_clear(struct rte_cryptodev_sym_session *sess, bool is_session_less) struct cnxk_se_sess *sess_priv = (struct cnxk_se_sess *)sess; /* Trigger CTX flush + invalidate to remove from CTX_CACHE */ - if (roc_errata_cpt_hang_on_mixed_ctx_val()) + if (hw_ctx_cache_enable()) roc_cpt_lf_ctx_flush(sess_priv->lf, &sess_priv->roc_se_ctx.se_ctx, true); if (sess_priv->roc_se_ctx.auth_key != NULL) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h index b1a40e8e25..6ee4cbda70 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h @@ -13,6 +13,7 @@ #include "roc_constants.h" #include "roc_cpt.h" #include "roc_cpt_sg.h" +#include "roc_errata.h" #include "roc_se.h" #define CNXK_CPT_MIN_HEADROOM_REQ 32 @@ -180,4 +181,11 @@ alloc_op_meta(struct roc_se_buf_ptr *buf, int32_t len, struct rte_mempool *cpt_m return mdata; } + +static __rte_always_inline bool +hw_ctx_cache_enable(void) +{ + return roc_errata_cpt_hang_on_mixed_ctx_val() || roc_model_is_cn10ka_b0() || + roc_model_is_cn10kb_a0(); +} #endif /* _CNXK_CRYPTODEV_OPS_H_ */ -- 2.25.1