From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0B5B442D82; Wed, 28 Jun 2023 19:19:11 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4D7DA42C4D; Wed, 28 Jun 2023 19:19:01 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7D26E42D1D for ; Wed, 28 Jun 2023 19:18:59 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35SE8AZd010660 for ; Wed, 28 Jun 2023 10:18:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=vsK391z92Fesi8DJ+KltjnU5EGSPDeLth148FQ+jl2U=; b=LMXFGjp250/i8Z5At16z98qvK2quu0S18LgV8AuPRLqO5PIm0iZkMeV+StV2oFh4LqrK 2goeJEXcKIsfHnDcaquc8yVuUOl/uEQ2EtYWqjt39+XYU/f1QpZiZzJFNf40eRb4vXq5 A2E0TbK50no4nRZCNZ2YDNm5ojAoIHFqKu0jGK+0IaPM8rLeS+gdhqlA60rJkOhWSkRt Uvy3KvpZjecqS6IuS6xceULDZq92ihghRqWaMfDZaf5egGHEq/a8Nq/7Odk1qVMr2/OQ eMfy/0Ixyr5VEiGEbkTN47rZnKKEFhruzJdqrs/eVc2RB2Wsr3hZTuKRreCs8BHfHOAA GQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3rgcugjxgu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 28 Jun 2023 10:18:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 28 Jun 2023 10:18:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 28 Jun 2023 10:18:56 -0700 Received: from localhost.localdomain (unknown [10.28.36.157]) by maili.marvell.com (Postfix) with ESMTP id 044193F7085; Wed, 28 Jun 2023 10:18:54 -0700 (PDT) From: Amit Prakash Shukla To: Vamsi Attunuru CC: , , Amit Prakash Shukla , Radha Mohan Chintakuntla Subject: [PATCH 4/7] dma/cnxk: update func field based on transfer type Date: Wed, 28 Jun 2023 22:48:31 +0530 Message-ID: <20230628171834.771431-4-amitprakashs@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230628171834.771431-1-amitprakashs@marvell.com> References: <20230628171834.771431-1-amitprakashs@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 2ZR1hu-FROGsYql7ZT3gp_K2b4FPiYAs X-Proofpoint-ORIG-GUID: 2ZR1hu-FROGsYql7ZT3gp_K2b4FPiYAs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-28_12,2023-06-27_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use pfid and vfid of src_port for incoming DMA transfers and dst_port for outgoing DMA transfers. Signed-off-by: Radha Mohan Chintakuntla Signed-off-by: Amit Prakash Shukla --- drivers/dma/cnxk/cnxk_dmadev.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c index 1dc124e68f..d8cfb98cd7 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.c +++ b/drivers/dma/cnxk/cnxk_dmadev.c @@ -84,13 +84,21 @@ cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, header->cn9k.xtype = DPI_XTYPE_INBOUND; header->cn9k.lport = conf->src_port.pcie.coreid; header->cn9k.fport = 0; - header->cn9k.pvfe = 1; + header->cn9k.pvfe = conf->src_port.pcie.vfen; + if (header->cn9k.pvfe) { + header->cn9k.func = conf->src_port.pcie.pfid << 12; + header->cn9k.func |= conf->src_port.pcie.vfid; + } break; case RTE_DMA_DIR_MEM_TO_DEV: header->cn9k.xtype = DPI_XTYPE_OUTBOUND; header->cn9k.lport = 0; header->cn9k.fport = conf->dst_port.pcie.coreid; - header->cn9k.pvfe = 1; + header->cn9k.pvfe = conf->dst_port.pcie.vfen; + if (header->cn9k.pvfe) { + header->cn9k.func = conf->dst_port.pcie.pfid << 12; + header->cn9k.func |= conf->dst_port.pcie.vfid; + } break; case RTE_DMA_DIR_MEM_TO_MEM: header->cn9k.xtype = DPI_XTYPE_INTERNAL_ONLY; @@ -102,6 +110,7 @@ cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, header->cn9k.xtype = DPI_XTYPE_EXTERNAL_ONLY; header->cn9k.lport = conf->src_port.pcie.coreid; header->cn9k.fport = conf->dst_port.pcie.coreid; + header->cn9k.pvfe = 0; }; max_desc = conf->nb_desc; @@ -159,13 +168,21 @@ cn10k_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, header->cn10k.xtype = DPI_XTYPE_INBOUND; header->cn10k.lport = conf->src_port.pcie.coreid; header->cn10k.fport = 0; - header->cn10k.pvfe = 1; + header->cn10k.pvfe = conf->src_port.pcie.vfen; + if (header->cn10k.pvfe) { + header->cn10k.func = conf->src_port.pcie.pfid << 12; + header->cn10k.func |= conf->src_port.pcie.vfid; + } break; case RTE_DMA_DIR_MEM_TO_DEV: header->cn10k.xtype = DPI_XTYPE_OUTBOUND; header->cn10k.lport = 0; header->cn10k.fport = conf->dst_port.pcie.coreid; - header->cn10k.pvfe = 1; + header->cn10k.pvfe = conf->dst_port.pcie.vfen; + if (header->cn10k.pvfe) { + header->cn10k.func = conf->dst_port.pcie.pfid << 12; + header->cn10k.func |= conf->dst_port.pcie.vfid; + } break; case RTE_DMA_DIR_MEM_TO_MEM: header->cn10k.xtype = DPI_XTYPE_INTERNAL_ONLY; @@ -177,6 +194,7 @@ cn10k_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, header->cn10k.xtype = DPI_XTYPE_EXTERNAL_ONLY; header->cn10k.lport = conf->src_port.pcie.coreid; header->cn10k.fport = conf->dst_port.pcie.coreid; + header->cn10k.pvfe = 0; }; max_desc = conf->nb_desc; -- 2.25.1