From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1184742FC1; Thu, 3 Aug 2023 09:52:04 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7EAC343279; Thu, 3 Aug 2023 09:51:30 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id 295EA43279 for ; Thu, 3 Aug 2023 09:51:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1691049088; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3c9i3+vq2QJ5bLDNCkFUrHapZ9Cuy6HH5mNjhNhztlU=; b=fb3qcOvY74ysSFb0rpfX8iG6eESZyKnFmkrWJalPz68kEyOTjwdP56aZP+ptIZ7TaioVGe TZ8JP5nNdE0oGpRZUdig2rtcxusDGnVobnLyC/hsJ35H+YJJ39mCxrdwO3BKKIfl4sSINA 40IAYyvZCw5LX0SJpw4aXyFlh9KoBiY= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-387-VZHY7nWHMomk4Eh6l6D3Bg-1; Thu, 03 Aug 2023 03:51:23 -0400 X-MC-Unique: VZHY7nWHMomk4Eh6l6D3Bg-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id DF3E289F703; Thu, 3 Aug 2023 07:51:22 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.224.120]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8F7A3C5796B; Thu, 3 Aug 2023 07:51:21 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com, nipun.gupta@amd.com, Timothy McDaniel , Gaetan Rivet Subject: [PATCH 10/14] pci: define some extended capability constants Date: Thu, 3 Aug 2023 09:50:33 +0200 Message-ID: <20230803075038.307012-11-david.marchand@redhat.com> In-Reply-To: <20230803075038.307012-1-david.marchand@redhat.com> References: <20230803075038.307012-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define some PCI extended capability constants and use them in existing drivers. Signed-off-by: David Marchand --- drivers/event/dlb2/pf/dlb2_main.c | 7 ++----- lib/pci/rte_pci.h | 2 ++ 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index 8d960edef6..29e3001627 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -27,9 +27,6 @@ #define NO_OWNER_VF 0 /* PF ONLY! */ #define NOT_VF_REQ false /* PF ONLY! */ -#define DLB2_PCI_EXT_CAP_ID_PRI 0x13 -#define DLB2_PCI_EXT_CAP_ID_ACS 0xD - #define DLB2_PCI_PRI_CTRL_ENABLE 0x1 #define DLB2_PCI_PRI_ALLOC_REQ 0xC #define DLB2_PCI_PRI_CTRL 0x4 @@ -263,7 +260,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) if (rte_pci_read_config(pdev, &slt_word2, 2, off) != 2) slt_word2 = 0; - off = DLB2_PCI_EXT_CAP_ID_PRI; + off = RTE_PCI_EXT_CAP_ID_PRI; pri_cap_offset = rte_pci_find_ext_capability(pdev, off); if (pri_cap_offset >= 0) { @@ -490,7 +487,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } - off = DLB2_PCI_EXT_CAP_ID_ACS; + off = RTE_PCI_EXT_CAP_ID_ACS; acs_cap_offset = rte_pci_find_ext_capability(pdev, off); if (acs_cap_offset >= 0) { diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index a83f6abe14..67b34a0af2 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -96,7 +96,9 @@ extern "C" { #define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ #define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ +#define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services */ #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV*/ +#define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ /* Single Root I/O Virtualization */ #define RTE_PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ -- 2.41.0