From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 649A642FC1; Thu, 3 Aug 2023 09:51:46 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4F5B143274; Thu, 3 Aug 2023 09:51:18 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id E32BD43267 for ; Thu, 3 Aug 2023 09:51:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1691049076; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eVnhlF0BNBFYd3LQfmmjGeo1WXVHECnYk1Efg646we8=; b=V/36liasJlBSEMOGQvZuUepy8wkPQOi+Y5iujgmsASG9HW2GQOyrpzFm1nlDQ7kFUlpiWw 4TNVnKNGpBzla98JFUWEay17W/ZBSsgHHyX6fYkucok4JdeLYGBdx52sOoIPZSJ7LFUmfV DQ5GmmTh5h4Ag2RfUdCYDcFyQXwmI0s= Received: from mimecast-mx02.redhat.com (66.187.233.73 [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-249-zZczp4XOOcW204eM8KgzvQ-1; Thu, 03 Aug 2023 03:51:13 -0400 X-MC-Unique: zZczp4XOOcW204eM8KgzvQ-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id B1EB03811F41; Thu, 3 Aug 2023 07:51:12 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.224.120]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6619AC5796C; Thu, 3 Aug 2023 07:51:11 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com, nipun.gupta@amd.com, Anatoly Burakov , Gaetan Rivet Subject: [PATCH 07/14] pci: define some BAR constants Date: Thu, 3 Aug 2023 09:50:30 +0200 Message-ID: <20230803075038.307012-8-david.marchand@redhat.com> In-Reply-To: <20230803075038.307012-1-david.marchand@redhat.com> References: <20230803075038.307012-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define some PCI BAR constants and use them in existing drivers. Signed-off-by: David Marchand --- drivers/bus/pci/linux/pci_vfio.c | 7 +++---- lib/pci/rte_pci.h | 4 ++++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c index f96b3ce7fb..c2e3d2f4b5 100644 --- a/drivers/bus/pci/linux/pci_vfio.c +++ b/drivers/bus/pci/linux/pci_vfio.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include @@ -430,14 +429,14 @@ pci_vfio_is_ioport_bar(const struct rte_pci_device *dev, int vfio_dev_fd, } ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar), - offset + PCI_BASE_ADDRESS_0 + bar_index * 4); + offset + RTE_PCI_BASE_ADDRESS_0 + bar_index * 4); if (ret != sizeof(ioport_bar)) { RTE_LOG(ERR, EAL, "Cannot read command (%x) from config space!\n", - PCI_BASE_ADDRESS_0 + bar_index*4); + RTE_PCI_BASE_ADDRESS_0 + bar_index*4); return -1; } - return (ioport_bar & PCI_BASE_ADDRESS_SPACE_IO) != 0; + return (ioport_bar & RTE_PCI_BASE_ADDRESS_SPACE_IO) != 0; } static int diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index bf2b2639f4..429904cff9 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -43,6 +43,10 @@ extern "C" { #define RTE_PCI_STATUS 0x06 /* 16 bits */ #define RTE_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ +/* Base addresses */ +#define RTE_PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ +#define RTE_PCI_BASE_ADDRESS_SPACE_IO 0x01 + /* Capability registers */ #define RTE_PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ #define RTE_PCI_CAP_ID_PM 0x01 /* Power Management */ -- 2.41.0