From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D6A7343011; Wed, 9 Aug 2023 03:33:43 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 48E64410FD; Wed, 9 Aug 2023 03:33:33 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 9302D43255 for ; Wed, 9 Aug 2023 03:33:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691544810; x=1723080810; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6EdDKPGNlIlhL7Q+OOODX7tyuiw8nTCWKBlwT/w94KM=; b=LDIdjIxhJZcO6LvRsOtsZbl063fPlaNEDIWGDzx0dcehpz6IlkO0i/vU vkXDImXJ8db1FZ9bGne+CwuEkL1GeAVECWAaOmaj6prFzB6+G+7w+OIL6 YLfqBuzKHNyHlNUbra+aABxzwHq4ahrYpVS/DWRFrAJAlQXaIxiaZQcYx X3Z6/ub4Stg9LadX4rKeRB/Uko0PKzTmVPggI6ogCHT/hxX/Shn+9tjOA CCnUIsPGfkx6OXyfTUWJqWJo/4GGsBwc3GaSchT87vD+7uOCHDQOB5J7J pfXd7pj7FQVp7TXg56F3oM8BoaH2cuRiASNKTAa1AzrDWtma/Ejz/v2cx A==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="374704463" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="374704463" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 18:33:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="845735065" X-IronPort-AV: E=Sophos;i="6.01,157,1684825200"; d="scan'208";a="845735065" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.75]) by fmsmga002.fm.intel.com with ESMTP; 08 Aug 2023 18:33:27 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, wenjing.qiao@intel.com, Simei Su , Milena Olech Subject: [PATCH 03/14] common/idpf/base: initial PTP support Date: Wed, 9 Aug 2023 01:32:57 +0000 Message-Id: <20230809013308.1449103-4-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809013308.1449103-1-wenjing.qiao@intel.com> References: <20230809013308.1449103-1-wenjing.qiao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Simei Su Adding a few PTP capabilities to determine which PTP features are enabled - legacy cross time, ptm, device clock control, PTP Tx timestamp with direct registers access, PTP Tx timestamp using virtchnl messages. Creating structures and opcodes to support feautres introduced by capabilities. Signed-off-by: Milena Olech Signed-off-by: Simei Su --- drivers/common/idpf/base/virtchnl2.h | 145 +++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index c49e4b943c..320430df6f 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -98,6 +98,9 @@ #define VIRTCHNL2_OP_ADD_QUEUE_GROUPS 538 #define VIRTCHNL2_OP_DEL_QUEUE_GROUPS 539 #define VIRTCHNL2_OP_GET_PORT_STATS 540 + /* TimeSync opcodes */ +#define VIRTCHNL2_OP_GET_PTP_CAPS 541 +#define VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES 542 #define VIRTCHNL2_RDMA_INVALID_QUEUE_IDX 0xFFFF @@ -1395,6 +1398,112 @@ struct virtchnl2_promisc_info { VIRTCHNL2_CHECK_STRUCT_LEN(8, virtchnl2_promisc_info); +/* VIRTCHNL2_PTP_CAPS + * PTP capabilities + */ +#define VIRTCHNL2_PTP_CAP_LEGACY_CROSS_TIME BIT(0) +#define VIRTCHNL2_PTP_CAP_PTM BIT(1) +#define VIRTCHNL2_PTP_CAP_DEVICE_CLOCK_CONTROL BIT(2) +#define VIRTCHNL2_PTP_CAP_TX_TSTAMPS_DIRECT BIT(3) +#define VIRTCHNL2_PTP_CAP_TX_TSTAMPS_VIRTCHNL BIT(4) + +/* Legacy cross time registers offsets */ +struct virtchnl2_ptp_legacy_cross_time_reg { + __le32 shadow_time_0; + __le32 shadow_time_l; + __le32 shadow_time_h; + __le32 cmd_sync; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_legacy_cross_time_reg); + +/* PTM cross time registers offsets */ +struct virtchnl2_ptp_ptm_cross_time_reg { + __le32 art_l; + __le32 art_h; + __le32 cmd_sync; + u8 pad[4]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_ptm_cross_time_reg); + +/* Registers needed to control the main clock */ +struct virtchnl2_ptp_device_clock_control { + __le32 cmd; + __le32 incval_l; + __le32 incval_h; + __le32 shadj_l; + __le32 shadj_h; + u8 pad[4]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_device_clock_control); + +/* Structure that defines tx tstamp entry - index and register offset */ +struct virtchnl2_ptp_tx_tstamp_entry { + __le32 tx_latch_register_base; + __le32 tx_latch_register_offset; + u8 index; + u8 pad[7]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_tx_tstamp_entry); + +/* Structure that defines tx tstamp entries - total number of latches + * and the array of entries. + */ +struct virtchnl2_ptp_tx_tstamp { + __le16 num_latches; + /* latch size expressed in bits */ + __le16 latch_size; + u8 pad[4]; + struct virtchnl2_ptp_tx_tstamp_entry ptp_tx_tstamp_entries[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_tx_tstamp); + +/* VIRTCHNL2_OP_GET_PTP_CAPS + * PV/VF sends this message to negotiate PTP capabilities. CP updates bitmap + * with supported features and fulfills appropriate structures. + */ +struct virtchnl2_get_ptp_caps { + /* PTP capability bitmap */ + /* see VIRTCHNL2_PTP_CAPS definitions */ + __le32 ptp_caps; + u8 pad[4]; + + struct virtchnl2_ptp_legacy_cross_time_reg legacy_cross_time_reg; + struct virtchnl2_ptp_ptm_cross_time_reg ptm_cross_time_reg; + struct virtchnl2_ptp_device_clock_control device_clock_control; + struct virtchnl2_ptp_tx_tstamp tx_tstamp; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(88, virtchnl2_get_ptp_caps); + +/* Structure that describes tx tstamp values, index and validity */ +struct virtchnl2_ptp_tx_tstamp_latch { + __le32 tstamp_h; + __le32 tstamp_l; + u8 index; + u8 valid; + u8 pad[6]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_ptp_tx_tstamp_latch); + +/* VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES + * PF/VF sends this message to receive a specified number of timestamps + * entries. + */ +struct virtchnl2_ptp_tx_tstamp_latches { + __le16 num_latches; + /* latch size expressed in bits */ + __le16 latch_size; + u8 pad[4]; + struct virtchnl2_ptp_tx_tstamp_latch tstamp_latches[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(24, virtchnl2_ptp_tx_tstamp_latches); static inline const char *virtchnl2_op_str(__le32 v_opcode) { @@ -1463,6 +1572,10 @@ static inline const char *virtchnl2_op_str(__le32 v_opcode) return "VIRTCHNL2_OP_DEL_QUEUE_GROUPS"; case VIRTCHNL2_OP_GET_PORT_STATS: return "VIRTCHNL2_OP_GET_PORT_STATS"; + case VIRTCHNL2_OP_GET_PTP_CAPS: + return "VIRTCHNL2_OP_GET_PTP_CAPS"; + case VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES: + return "VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES"; default: return "Unsupported (update virtchnl2.h)"; } @@ -1732,6 +1845,38 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 break; case VIRTCHNL2_OP_RESET_VF: break; + case VIRTCHNL2_OP_GET_PTP_CAPS: + valid_len = sizeof(struct virtchnl2_get_ptp_caps); + + if (msglen >= valid_len) { + struct virtchnl2_get_ptp_caps *ptp_caps = + (struct virtchnl2_get_ptp_caps *)msg; + + if (ptp_caps->tx_tstamp.num_latches == 0) { + err_msg_format = true; + break; + } + + valid_len += ((ptp_caps->tx_tstamp.num_latches - 1) * + sizeof(struct virtchnl2_ptp_tx_tstamp_entry)); + } + break; + case VIRTCHNL2_OP_GET_PTP_TX_TSTAMP_LATCHES: + valid_len = sizeof(struct virtchnl2_ptp_tx_tstamp_latches); + + if (msglen >= valid_len) { + struct virtchnl2_ptp_tx_tstamp_latches *tx_tstamp_latches = + (struct virtchnl2_ptp_tx_tstamp_latches *)msg; + + if (tx_tstamp_latches->num_latches == 0) { + err_msg_format = true; + break; + } + + valid_len += ((tx_tstamp_latches->num_latches - 1) * + sizeof(struct virtchnl2_ptp_tx_tstamp_latch)); + } + break; /* These are always errors coming from the VF. */ case VIRTCHNL2_OP_EVENT: case VIRTCHNL2_OP_UNKNOWN: -- 2.34.1