From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 090D243014; Wed, 9 Aug 2023 06:58:56 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EB7ED43249; Wed, 9 Aug 2023 06:58:50 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id B82A0400D6 for ; Wed, 9 Aug 2023 06:58:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691557129; x=1723093129; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ChrWgrLu/Z+IXTu6Xow1ZrXquqEPPfPIRiGtD6t9SSQ=; b=klvrtySYTj5Gl5uwifNTYCH1rTzF0uYCaPd2/DrqpD/jNzZDHBR5nUiu y2+2l/JFEHzooKid1909XbAR7tEPLMpwxyDCeqhroCdvmO0J8AWkvvlG3 Sc5tXODR9xGwN7VWiJ5brvuYLJP6TzuclfKpHnraXpIBnhNILva+iPimS M7qd5/AuCny/RrPSoKaj8o5kyaBGStNKPGGm/xhG5pM6cVdgUvzjmEK1u kLl+vB2lxmmu70XFkAldS5ziwLP5nvD+sgYFR/pMxVteOR130AZfXpsMl VPC9BsOPfjiADN/zmL9MVMh5x3GrazeCTCC/jzxp+u97uMsQ8ehHgJrb6 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="351329510" X-IronPort-AV: E=Sophos;i="6.01,158,1684825200"; d="scan'208";a="351329510" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2023 21:58:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10795"; a="821684808" X-IronPort-AV: E=Sophos;i="6.01,158,1684825200"; d="scan'208";a="821684808" Received: from unknown (HELO npg-dpdk-simeisu-cvl-119d218.sh.intel.com) ([10.67.119.108]) by FMSMGA003.fm.intel.com with ESMTP; 08 Aug 2023 21:58:47 -0700 From: Simei Su To: thomas@monjalon.net, ferruh.yigit@amd.com, andrew.rybchenko@oktetlabs.ru, kirill.rybalchenko@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, wenjun1.wu@intel.com, Simei Su Subject: [PATCH 1/3] ethdev: add frequency adjustment API Date: Wed, 9 Aug 2023 13:06:58 +0800 Message-Id: <20230809050700.271534-2-simei.su@intel.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20230809050700.271534-1-simei.su@intel.com> References: <20230809050700.271534-1-simei.su@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch introduces a new timesync API "rte_eth_timesync_adjust_fine" which enables finer adjustment of the PHC clock. During PTP timesync, "rte_eth_timesync_adjust_time" focuses on phase adjustment while "rte_eth_timesync_adjust_fine" focuses on frequency adjustment. This new function gets the scaled_ppm (desired frequency offset from nominal frequency in parts per million, but with a 16 bit binary fractional field). Signed-off-by: Simei Su Signed-off-by: Wenjun Wu --- lib/ethdev/ethdev_driver.h | 5 +++++ lib/ethdev/ethdev_trace.h | 9 +++++++++ lib/ethdev/ethdev_trace_points.c | 3 +++ lib/ethdev/rte_ethdev.c | 19 +++++++++++++++++++ lib/ethdev/rte_ethdev.h | 38 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 74 insertions(+) diff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h index 980f837..4c39c3d 100644 --- a/lib/ethdev/ethdev_driver.h +++ b/lib/ethdev/ethdev_driver.h @@ -636,6 +636,9 @@ typedef int (*eth_timesync_read_tx_timestamp_t)(struct rte_eth_dev *dev, /** @internal Function used to adjust the device clock. */ typedef int (*eth_timesync_adjust_time)(struct rte_eth_dev *dev, int64_t); +/** @internal Function used to adjust the clock increment rate. */ +typedef int (*eth_timesync_adjust_fine)(struct rte_eth_dev *dev, int64_t); + /** @internal Function used to get time from the device clock. */ typedef int (*eth_timesync_read_time)(struct rte_eth_dev *dev, struct timespec *timestamp); @@ -1347,6 +1350,8 @@ struct eth_dev_ops { eth_timesync_read_tx_timestamp_t timesync_read_tx_timestamp; /** Adjust the device clock */ eth_timesync_adjust_time timesync_adjust_time; + /** Adjust the clock increment rate */ + eth_timesync_adjust_fine timesync_adjust_fine; /** Get the device clock time */ eth_timesync_read_time timesync_read_time; /** Set the device clock time */ diff --git a/lib/ethdev/ethdev_trace.h b/lib/ethdev/ethdev_trace.h index 423e712..d613eb2 100644 --- a/lib/ethdev/ethdev_trace.h +++ b/lib/ethdev/ethdev_trace.h @@ -2175,6 +2175,15 @@ RTE_TRACE_POINT_FP( rte_trace_point_emit_int(ret); ) +/* Called in loop in examples/ptpclient */ +RTE_TRACE_POINT_FP( + rte_eth_trace_timesync_adjust_fine, + RTE_TRACE_POINT_ARGS(uint16_t port_id, int64_t scaled_ppm, int ret), + rte_trace_point_emit_u16(port_id); + rte_trace_point_emit_i64(scaled_ppm); + rte_trace_point_emit_int(ret); +) + /* Called in loop in app/test-flow-perf */ RTE_TRACE_POINT_FP( rte_flow_trace_create, diff --git a/lib/ethdev/ethdev_trace_points.c b/lib/ethdev/ethdev_trace_points.c index 91f71d8..eb539bb 100644 --- a/lib/ethdev/ethdev_trace_points.c +++ b/lib/ethdev/ethdev_trace_points.c @@ -406,6 +406,9 @@ RTE_TRACE_POINT_REGISTER(rte_eth_trace_timesync_read_tx_timestamp, RTE_TRACE_POINT_REGISTER(rte_eth_trace_timesync_adjust_time, lib.ethdev.timesync_adjust_time) +RTE_TRACE_POINT_REGISTER(rte_eth_trace_timesync_adjust_fine, + lib.ethdev.timesync_adjust_fine) + RTE_TRACE_POINT_REGISTER(rte_eth_trace_timesync_read_time, lib.ethdev.timesync_read_time) diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index 0840d2b..7b75214 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -6109,6 +6109,25 @@ rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta) } int +rte_eth_timesync_adjust_fine(uint16_t port_id, int64_t scaled_ppm) +{ + struct rte_eth_dev *dev; + int ret; + + RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); + dev = &rte_eth_devices[port_id]; + + if (*dev->dev_ops->timesync_adjust_fine == NULL) + return -ENOTSUP; + ret = eth_err(port_id, (*dev->dev_ops->timesync_adjust_fine)(dev, + scaled_ppm)); + + rte_eth_trace_timesync_adjust_fine(port_id, scaled_ppm, ret); + + return ret; +} + +int rte_eth_timesync_read_time(uint16_t port_id, struct timespec *timestamp) { struct rte_eth_dev *dev; diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index 3d44979..78fc07c 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -5145,6 +5145,44 @@ int rte_eth_timesync_read_tx_timestamp(uint16_t port_id, int rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta); /** + * Adjust the frequency of the PHC cycle counter by the indicated amount + * from the base frequency. + * + * This function is used to do hardware timestamp adjustment in fine + * granularity. It can be used in conjunction with rte_eth_timesync_adjust_time + * to do more precise time control. + * + * E.g, below is a simple usage: + * if master offset > master offset threshold + * do rte_eth_timesync_adjust_time; + * else + * do rte_eth_timesync_adjust_fine; + * + * The user can apply a control algorithm to leverage these two APIs, one + * example is in dpdk-ptpclient. + * + * This API is implemented with the below basic logic: + * - Determine a base frequency value + * - Multiply this by the abs() of the requested adjustment, then divide by + * the appropriate divisor (65536 billion). + * - Add or subtract this difference from the base frequency to calculate a + * new adjustment. + * + * @param port_id + * The port identifier of the Ethernet device. + * @param scaled_ppm + * Desired frequency change in scaled parts per million. Scaled parts per + * million is ppm with a 16-bit binary fractional field. + * + * @return + * - 0: Success. + * - -ENODEV: The port ID is invalid. + * - -EIO: if device is removed. + * - -ENOTSUP: The function is not supported by the Ethernet driver. + */ +int rte_eth_timesync_adjust_fine(uint16_t port_id, int64_t scaled_ppm); + +/** * Read the time from the timesync clock on an Ethernet device. * * This is usually used in conjunction with other Ethdev timesync functions to -- 2.9.5