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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D9.mail.protection.outlook.com (10.167.241.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6652.20 via Frontend Transport; Sat, 12 Aug 2023 00:57:51 +0000 Received: from BLR-5CG134626B.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 11 Aug 2023 19:57:49 -0500 From: Vipin Varghese To: , CC: Subject: [PATCH] usertools: suggest use of hwloc for new cpu Date: Sat, 12 Aug 2023 06:27:20 +0530 Message-ID: <20230812005720.997-1-vipin.varghese@amd.com> X-Mailer: git-send-email 2.41.0.windows.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D9:EE_|MW4PR12MB7438:EE_ X-MS-Office365-Filtering-Correlation-Id: 7693e675-75a1-4561-d4c8-08db9acf2792 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2023 00:57:51.4805 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7693e675-75a1-4561-d4c8-08db9acf2792 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7438 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Most modern processor now supports numa by partitioning NUMA based on CPU-IO & Last Level Cache within the same socket. As per the discussion in mailing list, suggesting the make use of hw-loc for such scenarios. Signed-off-by: Vipin Varghese --- --- usertools/cpu_layout.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/usertools/cpu_layout.py b/usertools/cpu_layout.py index 891b9238fa..c8ac613878 100755 --- a/usertools/cpu_layout.py +++ b/usertools/cpu_layout.py @@ -29,6 +29,16 @@ core_map[key] = [] core_map[key].append(cpu) + +print("") +print(format("=" * (55 + len(base_path)))) +print(" for newer CPU, that supports sub Socket Numa & L3 Numa clustering, please use") +print(format("=" * (55 + len(base_path)))) +print(" - lstopo-no-graphics --no-io -.ascii (CPU Mapping)") +print(" - lstopo-no-graphics -.ascii --whole-io --no-caches (IO device Mapping)") +print(format("=" * (55 + len(base_path)))) +print("") + print(format("=" * (47 + len(base_path)))) print("Core and Socket Information (as reported by '{}')".format(base_path)) print("{}\n".format("=" * (47 + len(base_path)))) -- 2.34.1