From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 92914430C1; Mon, 21 Aug 2023 13:38:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4D6B4432A5; Mon, 21 Aug 2023 13:36:42 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id CDAB64324F for ; Mon, 21 Aug 2023 13:36:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1692617798; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=agVjOBKiT6JRZqj2dmI/CDTV24Zii0z0uvWHERpzBGU=; b=BSlRld6M/Y2Jyl8+Igcct43eht3+MFFYizsJP+RU7LDQ9h4KYPQgiB20l2Db9t4bFepjuW Srmzsoa5+XL0mkyAPIHZV+J3Y25UBcV/IicxhNxlltk2ZzVDQrA+w4IXS5C6C8XXa1HS9I XTBrNX9RPxB4QPY92L6Wn5FaoEkWhZQ= Received: from mimecast-mx02.redhat.com (66.187.233.73 [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-131-ir15BsacPdKkQmodj4oP6A-1; Mon, 21 Aug 2023 07:36:35 -0400 X-MC-Unique: ir15BsacPdKkQmodj4oP6A-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id ACCDF2A5955C; Mon, 21 Aug 2023 11:36:34 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.226.19]) by smtp.corp.redhat.com (Postfix) with ESMTP id EE88D40C2063; Mon, 21 Aug 2023 11:36:32 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com, nipun.gupta@amd.com, bruce.richardson@intel.com, Timothy McDaniel , Julien Aube , Gaetan Rivet Subject: [PATCH v2 10/15] pci: define some PCIe constants Date: Mon, 21 Aug 2023 13:35:43 +0200 Message-ID: <20230821113549.3191921-11-david.marchand@redhat.com> In-Reply-To: <20230821113549.3191921-1-david.marchand@redhat.com> References: <20230803075038.307012-1-david.marchand@redhat.com> <20230821113549.3191921-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define some PCI Express constants and use them in existing drivers. Signed-off-by: David Marchand Acked-by: Bruce Richardson --- drivers/event/dlb2/pf/dlb2_main.c | 40 ++++++++++++------------------- drivers/net/bnx2x/bnx2x.c | 16 ++++++------- drivers/net/bnx2x/bnx2x.h | 35 --------------------------- lib/pci/rte_pci.h | 21 +++++++++++++--- 4 files changed, 41 insertions(+), 71 deletions(-) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index 6dbaa2ff97..8d960edef6 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -27,16 +27,6 @@ #define NO_OWNER_VF 0 /* PF ONLY! */ #define NOT_VF_REQ false /* PF ONLY! */ -#define DLB2_PCI_LNKCTL 16 -#define DLB2_PCI_SLTCTL 24 -#define DLB2_PCI_RTCTL 28 -#define DLB2_PCI_EXP_DEVCTL2 40 -#define DLB2_PCI_LNKCTL2 48 -#define DLB2_PCI_SLTCTL2 56 -#define DLB2_PCI_EXP_DEVSTA 10 -#define DLB2_PCI_EXP_DEVSTA_TRPND 0x20 -#define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000 - #define DLB2_PCI_EXT_CAP_ID_PRI 0x13 #define DLB2_PCI_EXT_CAP_ID_ACS 0xD @@ -249,27 +239,27 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) if (rte_pci_read_config(pdev, &dev_ctl_word, 2, off) != 2) dev_ctl_word = 0; - off = pcie_cap_offset + DLB2_PCI_LNKCTL; + off = pcie_cap_offset + RTE_PCI_EXP_LNKCTL; if (rte_pci_read_config(pdev, &lnk_word, 2, off) != 2) lnk_word = 0; - off = pcie_cap_offset + DLB2_PCI_SLTCTL; + off = pcie_cap_offset + RTE_PCI_EXP_SLTCTL; if (rte_pci_read_config(pdev, &slt_word, 2, off) != 2) slt_word = 0; - off = pcie_cap_offset + DLB2_PCI_RTCTL; + off = pcie_cap_offset + RTE_PCI_EXP_RTCTL; if (rte_pci_read_config(pdev, &rt_ctl_word, 2, off) != 2) rt_ctl_word = 0; - off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL2; + off = pcie_cap_offset + RTE_PCI_EXP_DEVCTL2; if (rte_pci_read_config(pdev, &dev_ctl2_word, 2, off) != 2) dev_ctl2_word = 0; - off = pcie_cap_offset + DLB2_PCI_LNKCTL2; + off = pcie_cap_offset + RTE_PCI_EXP_LNKCTL2; if (rte_pci_read_config(pdev, &lnk_word2, 2, off) != 2) lnk_word2 = 0; - off = pcie_cap_offset + DLB2_PCI_SLTCTL2; + off = pcie_cap_offset + RTE_PCI_EXP_SLTCTL2; if (rte_pci_read_config(pdev, &slt_word2, 2, off) != 2) slt_word2 = 0; @@ -296,7 +286,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) for (wait_count = 0; wait_count < 4; wait_count++) { int sleep_time; - off = pcie_cap_offset + DLB2_PCI_EXP_DEVSTA; + off = pcie_cap_offset + RTE_PCI_EXP_DEVSTA; ret = rte_pci_read_config(pdev, &devsta_busy_word, 2, off); if (ret != 2) { DLB2_LOG_ERR("[%s()] failed to read the pci device status\n", @@ -304,7 +294,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return ret; } - if (!(devsta_busy_word & DLB2_PCI_EXP_DEVSTA_TRPND)) + if (!(devsta_busy_word & RTE_PCI_EXP_DEVSTA_TRPND)) break; sleep_time = (1 << (wait_count)) * 100; @@ -325,7 +315,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return ret; } - devctl_word |= DLB2_PCI_EXP_DEVCTL_BCR_FLR; + devctl_word |= RTE_PCI_EXP_DEVCTL_BCR_FLR; ret = rte_pci_write_config(pdev, &devctl_word, 2, off); if (ret != 2) { @@ -347,7 +337,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return ret; } - off = pcie_cap_offset + DLB2_PCI_LNKCTL; + off = pcie_cap_offset + RTE_PCI_EXP_LNKCTL; ret = rte_pci_write_config(pdev, &lnk_word, 2, off); if (ret != 2) { DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", @@ -355,7 +345,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return ret; } - off = pcie_cap_offset + DLB2_PCI_SLTCTL; + off = pcie_cap_offset + RTE_PCI_EXP_SLTCTL; ret = rte_pci_write_config(pdev, &slt_word, 2, off); if (ret != 2) { DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", @@ -363,7 +353,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return ret; } - off = pcie_cap_offset + DLB2_PCI_RTCTL; + off = pcie_cap_offset + RTE_PCI_EXP_RTCTL; ret = rte_pci_write_config(pdev, &rt_ctl_word, 2, off); if (ret != 2) { DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", @@ -371,7 +361,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return ret; } - off = pcie_cap_offset + DLB2_PCI_EXP_DEVCTL2; + off = pcie_cap_offset + RTE_PCI_EXP_DEVCTL2; ret = rte_pci_write_config(pdev, &dev_ctl2_word, 2, off); if (ret != 2) { DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", @@ -379,7 +369,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return ret; } - off = pcie_cap_offset + DLB2_PCI_LNKCTL2; + off = pcie_cap_offset + RTE_PCI_EXP_LNKCTL2; ret = rte_pci_write_config(pdev, &lnk_word2, 2, off); if (ret != 2) { DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", @@ -387,7 +377,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return ret; } - off = pcie_cap_offset + DLB2_PCI_SLTCTL2; + off = pcie_cap_offset + RTE_PCI_EXP_SLTCTL2; ret = rte_pci_write_config(pdev, &slt_word2, 2, off); if (ret != 2) { DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c index faf061beba..cfd8e35aa3 100644 --- a/drivers/net/bnx2x/bnx2x.c +++ b/drivers/net/bnx2x/bnx2x.c @@ -7630,8 +7630,8 @@ static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg) static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc) { - return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) & - PCIM_EXP_STA_TRANSACTION_PND; + return bnx2x_pcie_capability_read(sc, RTE_PCI_EXP_TYPE_RC_EC) & + RTE_PCI_EXP_DEVSTA_TRPND; } /* @@ -7658,11 +7658,11 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc) sc->devinfo.pcie_pm_cap_reg = caps->addr; } - link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA); + link_status = bnx2x_pcie_capability_read(sc, RTE_PCI_EXP_LNKSTA); - sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED); + sc->devinfo.pcie_link_speed = (link_status & RTE_PCI_EXP_LNKSTA_CLS); sc->devinfo.pcie_link_width = - ((link_status & PCIM_LINK_STA_WIDTH) >> 4); + ((link_status & RTE_PCI_EXP_LNKSTA_NLW) >> 4); PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d", sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width); @@ -9979,10 +9979,10 @@ static void bnx2x_init_pxp(struct bnx2x_softc *sc) uint16_t devctl; int r_order, w_order; - devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL); + devctl = bnx2x_pcie_capability_read(sc, RTE_PCI_EXP_DEVCTL); - w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5); - r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12); + w_order = ((devctl & RTE_PCI_EXP_DEVCTL_PAYLOAD) >> 5); + r_order = ((devctl & RTE_PCI_EXP_DEVCTL_READRQ) >> 12); ecore_init_pxp_arb(sc, r_order, w_order); } diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index 1efa166316..35206b4758 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -30,45 +30,10 @@ #include "elink.h" -#ifndef RTE_EXEC_ENV_FREEBSD -#include - -#define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC -#define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND -#define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA -#define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW -#define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS -#define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL -#define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD -#define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ -#else -#include -#endif - #define IFM_10G_CX4 20 /* 10GBase CX4 copper */ #define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */ #define IFM_10G_T 26 /* 10GBase-T - RJ45 */ -#ifndef RTE_EXEC_ENV_FREEBSD -#define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC -#define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND -#define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA -#define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW -#define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS -#define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL -#define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD -#define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ -#else -#define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA -#define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND -#define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA -#define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH -#define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED -#define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL -#define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD -#define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST -#endif - #ifndef ARRAY_SIZE #define ARRAY_SIZE(arr) RTE_DIM(arr) #endif diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 542d142dfb..a82f073a7d 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -63,6 +63,24 @@ extern "C" { #define RTE_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ #define RTE_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ +/* PCI Express capability registers (RTE_PCI_CAP_ID_EXP) */ +#define RTE_PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ +#define RTE_PCI_EXP_DEVCTL 0x08 /* Device Control */ +#define RTE_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ +#define RTE_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ +#define RTE_PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ +#define RTE_PCI_EXP_DEVSTA 0x0a /* Device Status */ +#define RTE_PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */ +#define RTE_PCI_EXP_LNKCTL 0x10 /* Link Control */ +#define RTE_PCI_EXP_LNKSTA 0x12 /* Link Status */ +#define RTE_PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ +#define RTE_PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ +#define RTE_PCI_EXP_SLTCTL 0x18 /* Slot Control */ +#define RTE_PCI_EXP_RTCTL 0x1c /* Root Control */ +#define RTE_PCI_EXP_DEVCTL2 0x28 /* Device Control 2 */ +#define RTE_PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */ +#define RTE_PCI_EXP_SLTCTL2 0x38 /* Slot Control 2 */ + /* MSI-X registers (RTE_PCI_CAP_ID_MSIX) */ #define RTE_PCI_MSIX_FLAGS 2 /* Message Control */ #define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff /* Table size */ @@ -73,9 +91,6 @@ extern "C" { #define RTE_PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */ #define RTE_PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */ -/* PCI Express capability registers */ -#define RTE_PCI_EXP_DEVCTL 8 /* Device Control */ - /* Extended Capabilities (PCI-X 2.0 and Express) */ #define RTE_PCI_EXT_CAP_ID(header) (header & 0x0000ffff) #define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) -- 2.41.0