From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5C07430DF; Wed, 23 Aug 2023 13:16:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BF9B043267; Wed, 23 Aug 2023 13:16:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 07D5C43272 for ; Wed, 23 Aug 2023 13:16:25 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37N6xVJr012908 for ; Wed, 23 Aug 2023 04:16:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=GzvVQ4ipAT526+ApxWWbTRP/k2AAJDNpIEowC6spNUI=; b=Ycf7Aa5ZN3xjK3mZEQlTzb4ItiprOcqWHwVhKXU5nAbRHVKXlAeeocAxm13ccRLDQzi0 48poZhwoojEFaZtMpZkkd8cpEWOIMoe+/b6erSTJ6GEygroIwY/S1tn0ozi8gfxD4wxz hxqgeIyd7jkqxTMHjr6akDVLxplJy+S1Brue76dp5n1T5p9htzoMoF2PJdX6cBBRLdex PMlN7FonT1lI5EUTnP1p1nKP/8+3RwOtxO9mqqU5KT3hVraSQDvH7VxxhlQnv9p3qS/L w6aBYHWbPiQSEecg4W4n30XaDAKKO/LztkIR8Oik1tG0lHQmfpyWde+TWPAX/7bWWDP1 9A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sn20ctmes-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 23 Aug 2023 04:16:25 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 23 Aug 2023 04:16:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 23 Aug 2023 04:16:23 -0700 Received: from localhost.localdomain (unknown [10.28.36.157]) by maili.marvell.com (Postfix) with ESMTP id 6B5273F708A; Wed, 23 Aug 2023 04:16:21 -0700 (PDT) From: Amit Prakash Shukla To: Vamsi Attunuru CC: , , Amit Prakash Shukla , Radha Mohan Chintakuntla Subject: [PATCH v5 08/12] dma/cnxk: update func field based on transfer type Date: Wed, 23 Aug 2023 16:45:21 +0530 Message-ID: <20230823111525.3975662-8-amitprakashs@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230823111525.3975662-1-amitprakashs@marvell.com> References: <20230821174942.3165191-1-amitprakashs@marvell.com> <20230823111525.3975662-1-amitprakashs@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 4Kpyr7opk1iHM25shOifiBRbjI6Pd_lJ X-Proofpoint-ORIG-GUID: 4Kpyr7opk1iHM25shOifiBRbjI6Pd_lJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-23_06,2023-08-22_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use pfid and vfid of src_port for incoming DMA transfers and dst_port for outgoing DMA transfers. Signed-off-by: Radha Mohan Chintakuntla Signed-off-by: Amit Prakash Shukla --- v2: - Fix for bugs observed in v1. - Squashed few commits. v3: - Resolved review suggestions. - Code improvement. v4: - Resolved checkpatch warnings. v5: - Updated commit message. - Split the commits. drivers/dma/cnxk/cnxk_dmadev.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c index b0de0cf215..4793c93ca8 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.c +++ b/drivers/dma/cnxk/cnxk_dmadev.c @@ -84,13 +84,21 @@ cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, header->cn9k.xtype = DPI_XTYPE_INBOUND; header->cn9k.lport = conf->src_port.pcie.coreid; header->cn9k.fport = 0; - header->cn9k.pvfe = 1; + header->cn9k.pvfe = conf->src_port.pcie.vfen; + if (header->cn9k.pvfe) { + header->cn9k.func = conf->src_port.pcie.pfid << 12; + header->cn9k.func |= conf->src_port.pcie.vfid; + } break; case RTE_DMA_DIR_MEM_TO_DEV: header->cn9k.xtype = DPI_XTYPE_OUTBOUND; header->cn9k.lport = 0; header->cn9k.fport = conf->dst_port.pcie.coreid; - header->cn9k.pvfe = 1; + header->cn9k.pvfe = conf->dst_port.pcie.vfen; + if (header->cn9k.pvfe) { + header->cn9k.func = conf->dst_port.pcie.pfid << 12; + header->cn9k.func |= conf->dst_port.pcie.vfid; + } break; case RTE_DMA_DIR_MEM_TO_MEM: header->cn9k.xtype = DPI_XTYPE_INTERNAL_ONLY; @@ -102,6 +110,7 @@ cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, header->cn9k.xtype = DPI_XTYPE_EXTERNAL_ONLY; header->cn9k.lport = conf->src_port.pcie.coreid; header->cn9k.fport = conf->dst_port.pcie.coreid; + header->cn9k.pvfe = 0; }; max_desc = conf->nb_desc; @@ -159,13 +168,21 @@ cn10k_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, header->cn10k.xtype = DPI_XTYPE_INBOUND; header->cn10k.lport = conf->src_port.pcie.coreid; header->cn10k.fport = 0; - header->cn10k.pvfe = 1; + header->cn10k.pvfe = conf->src_port.pcie.vfen; + if (header->cn10k.pvfe) { + header->cn10k.func = conf->src_port.pcie.pfid << 12; + header->cn10k.func |= conf->src_port.pcie.vfid; + } break; case RTE_DMA_DIR_MEM_TO_DEV: header->cn10k.xtype = DPI_XTYPE_OUTBOUND; header->cn10k.lport = 0; header->cn10k.fport = conf->dst_port.pcie.coreid; - header->cn10k.pvfe = 1; + header->cn10k.pvfe = conf->dst_port.pcie.vfen; + if (header->cn10k.pvfe) { + header->cn10k.func = conf->dst_port.pcie.pfid << 12; + header->cn10k.func |= conf->dst_port.pcie.vfid; + } break; case RTE_DMA_DIR_MEM_TO_MEM: header->cn10k.xtype = DPI_XTYPE_INTERNAL_ONLY; @@ -177,6 +194,7 @@ cn10k_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan, header->cn10k.xtype = DPI_XTYPE_EXTERNAL_ONLY; header->cn10k.lport = conf->src_port.pcie.coreid; header->cn10k.fport = conf->dst_port.pcie.coreid; + header->cn10k.pvfe = 0; }; max_desc = conf->nb_desc; -- 2.25.1