From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2B63542597; Thu, 14 Sep 2023 14:37:36 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 29DB640DDB; Thu, 14 Sep 2023 14:37:04 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mails.dpdk.org (Postfix) with ESMTP id ECF9140DDB for ; Thu, 14 Sep 2023 14:37:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1694695021; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LyIFbaH+8nMVjfGDzPThLGv+vweeBjKKuoJ/jxnU3AI=; b=PgzMPCjIgwil3cL8Ah0titng4k7fDcBRwz3j2UDoL0KT3cWe7QyWFeCNLklYl7WPotV70i gswo7GWtRwMvIdzSW/NodtKG/oSc6rzz8fXxwHmZCrezLX250uroF5XNVa7I9PGYCfTiNM GzOFlnOMNOf2dfEuube1B5vZYsdwKR0= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-384-KY2SffDzOEqTA6Di9GbFyw-1; Thu, 14 Sep 2023 08:36:57 -0400 X-MC-Unique: KY2SffDzOEqTA6Di9GbFyw-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 5509481DBE5; Thu, 14 Sep 2023 12:36:57 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.225.25]) by smtp.corp.redhat.com (Postfix) with ESMTP id DB9FC2026D68; Thu, 14 Sep 2023 12:36:55 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com, nipun.gupta@amd.com, bruce.richardson@intel.com, Julien Aube , Gaetan Rivet Subject: [PATCH v3 09/15] pci: define some PM constants Date: Thu, 14 Sep 2023 14:36:08 +0200 Message-ID: <20230914123615.1705654-10-david.marchand@redhat.com> In-Reply-To: <20230914123615.1705654-1-david.marchand@redhat.com> References: <20230803075038.307012-1-david.marchand@redhat.com> <20230914123615.1705654-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define some PCI Power Management constants and use them in existing drivers. Signed-off-by: David Marchand Acked-by: Bruce Richardson Reviewed-by: Chenbo Xia --- drivers/net/bnx2x/bnx2x.c | 17 +++++++++-------- drivers/net/bnx2x/bnx2x.h | 5 ----- lib/pci/rte_pci.h | 6 ++++++ 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c index e3f14400cc..faf061beba 100644 --- a/drivers/net/bnx2x/bnx2x.c +++ b/drivers/net/bnx2x/bnx2x.c @@ -5843,17 +5843,17 @@ static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state) return 0; } - pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr, + pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + RTE_PCI_PM_CTRL), &pmcsr, 2); switch (state) { case PCI_PM_D0: pci_write_word(sc, (sc->devinfo.pcie_pm_cap_reg + - PCIR_POWER_STATUS), - ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME)); + RTE_PCI_PM_CTRL), + ((pmcsr & ~RTE_PCI_PM_CTRL_STATE_MASK) | RTE_PCI_PM_CTRL_PME_STATUS)); - if (pmcsr & PCIM_PSTAT_DMASK) { + if (pmcsr & RTE_PCI_PM_CTRL_STATE_MASK) { /* delay required during transition out of D3hot */ DELAY(20000); } @@ -5866,16 +5866,17 @@ static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state) return 0; } - pmcsr &= ~PCIM_PSTAT_DMASK; - pmcsr |= PCIM_PSTAT_D3; + pmcsr &= ~RTE_PCI_PM_CTRL_STATE_MASK; + /* D3 power state */ + pmcsr |= 0x3; if (sc->wol) { - pmcsr |= PCIM_PSTAT_PMEENABLE; + pmcsr |= RTE_PCI_PM_CTRL_PME_ENABLE; } pci_write_long(sc, (sc->devinfo.pcie_pm_cap_reg + - PCIR_POWER_STATUS), pmcsr); + RTE_PCI_PM_CTRL), pmcsr); /* * No more memory access after this point until device is brought back diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index 60af75d336..1efa166316 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -41,11 +41,6 @@ #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ -#define PCIR_POWER_STATUS PCI_PM_CTRL -#define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK -#define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS -#define PCIM_PSTAT_D3 0x3 -#define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE #else #include #endif diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 12866be5d5..90d734f0ad 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -58,6 +58,12 @@ extern "C" { #define RTE_PCI_CAP_SIZEOF 4 #define RTE_PCI_CAP_NEXT 1 +/* Power Management Registers (RTE_PCI_CAP_ID_PM) */ +#define RTE_PCI_PM_CTRL 4 /* PM control and status register */ +#define RTE_PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ +#define RTE_PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ +#define RTE_PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ + /* MSI-X registers (RTE_PCI_CAP_ID_MSIX) */ #define RTE_PCI_MSIX_FLAGS 2 /* Message Control */ #define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff /* Table size */ -- 2.41.0