From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9CC3942597; Thu, 14 Sep 2023 14:38:03 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2DC644069F; Thu, 14 Sep 2023 14:37:17 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mails.dpdk.org (Postfix) with ESMTP id 9E05C40E09 for ; Thu, 14 Sep 2023 14:37:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1694695035; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=r+9s0tmSgLnA4lNt4XHMw2vlzBvYyPcg/ATe+8u9HLY=; b=A7eGhbRdiZP+i7jwgii1g+SPz2lKZuEnaq7ZIRFKq9cEVztlpbR7oYYcaPwr3yyAB01f9r 8qRi2fGd4N0q8K56+tquMuFl6K2QneIWsXLsKZw/Dr8ydXAbYK61cTMwjEXw4ofoaOQDWL cqgR7qvX02+R1xnbxCBF/SMKO/JkykM= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-6-1ChjG090Pp-Ewq-Kick_2Q-1; Thu, 14 Sep 2023 08:37:12 -0400 X-MC-Unique: 1ChjG090Pp-Ewq-Kick_2Q-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 4F558101CC61; Thu, 14 Sep 2023 12:37:11 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.225.25]) by smtp.corp.redhat.com (Postfix) with ESMTP id D59A710F1BE7; Thu, 14 Sep 2023 12:37:09 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com, nipun.gupta@amd.com, bruce.richardson@intel.com, Abdullah Sevincer , Gaetan Rivet Subject: [PATCH v3 13/15] pci: define some PRI constants Date: Thu, 14 Sep 2023 14:36:12 +0200 Message-ID: <20230914123615.1705654-14-david.marchand@redhat.com> In-Reply-To: <20230914123615.1705654-1-david.marchand@redhat.com> References: <20230803075038.307012-1-david.marchand@redhat.com> <20230914123615.1705654-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define some PCI PRI extended feature constants and use them in existing drivers. Signed-off-by: David Marchand Acked-by: Bruce Richardson --- drivers/event/dlb2/pf/dlb2_main.c | 11 ++++------- lib/pci/rte_pci.h | 5 +++++ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index 8e729d1964..187a356c24 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -27,9 +27,6 @@ #define NO_OWNER_VF 0 /* PF ONLY! */ #define NOT_VF_REQ false /* PF ONLY! */ -#define DLB2_PCI_PRI_CTRL_ENABLE 0x1 -#define DLB2_PCI_PRI_ALLOC_REQ 0xC -#define DLB2_PCI_PRI_CTRL 0x4 #define DLB2_PCI_ERR_ROOT_STATUS 0x30 #define DLB2_PCI_ERR_COR_STATUS 0x10 #define DLB2_PCI_ERR_UNCOR_STATUS 0x4 @@ -257,7 +254,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) pri_cap_offset = rte_pci_find_ext_capability(pdev, off); if (pri_cap_offset >= 0) { - off = pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ; + off = pri_cap_offset + RTE_PCI_PRI_ALLOC_REQ; if (rte_pci_read_config(pdev, &pri_reqs_dword, 4, off) != 4) pri_reqs_dword = 0; } @@ -377,9 +374,9 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } if (pri_cap_offset >= 0) { - pri_ctrl_word = DLB2_PCI_PRI_CTRL_ENABLE; + pri_ctrl_word = RTE_PCI_PRI_CTRL_ENABLE; - off = pri_cap_offset + DLB2_PCI_PRI_ALLOC_REQ; + off = pri_cap_offset + RTE_PCI_PRI_ALLOC_REQ; ret = rte_pci_write_config(pdev, &pri_reqs_dword, 4, off); if (ret != 4) { DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", @@ -387,7 +384,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return ret; } - off = pri_cap_offset + DLB2_PCI_PRI_CTRL; + off = pri_cap_offset + RTE_PCI_PRI_CTRL; ret = rte_pci_write_config(pdev, &pri_ctrl_word, 2, off); if (ret != 2) { DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index a6c52a232d..6bbcad20f2 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -123,6 +123,11 @@ extern "C" { #define RTE_PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ #define RTE_PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ +/* Page Request Interface (RTE_PCI_EXT_CAP_ID_PRI) */ +#define RTE_PCI_PRI_CTRL 0x04 /* PRI control register */ +#define RTE_PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */ +#define RTE_PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ + /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */ #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8 #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X") -- 2.41.0