From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D760142597; Thu, 14 Sep 2023 14:37:05 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 13474406FF; Thu, 14 Sep 2023 14:36:52 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id 783ED406FF for ; Thu, 14 Sep 2023 14:36:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1694695010; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jRVNFr9PreRFFcAf2TR4k+BvH2uHmIaM2IPPDQcYgyw=; b=bPFAhZu/Usk8JQk/Kwha4BGi2ce/MYRH3AENNmm6jMxuIHsIJhaQQDflul1KsFOpgt7OnC EDXaz84uWT1ph9xaOcjdQFe9DShVG7v5hvXwP7rfBEABI6sLMby16SnKAEuFPXII91C9AQ lbjZ66V2BfHKsPWlKp9lSarLHhRvXQE= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-599-E5wuUDXnORWUPcST2xd4gg-1; Thu, 14 Sep 2023 08:36:43 -0400 X-MC-Unique: E5wuUDXnORWUPcST2xd4gg-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id ED707101FAA3; Thu, 14 Sep 2023 12:36:41 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.225.25]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9A44921B2413; Thu, 14 Sep 2023 12:36:38 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com, nipun.gupta@amd.com, bruce.richardson@intel.com, Anatoly Burakov , Jay Zhou , Abdullah Sevincer , Julien Aube , Rahul Lakkireddy , Junfeng Guo , Jeroen de Borst , Rushil Gupta , Joshua Washington , Dongdong Liu , Yisen Zhuang , Maxime Coquelin , Xiao Wang , Gaetan Rivet Subject: [PATCH v3 05/15] pci: define some capability constants Date: Thu, 14 Sep 2023 14:36:04 +0200 Message-ID: <20230914123615.1705654-6-david.marchand@redhat.com> In-Reply-To: <20230914123615.1705654-1-david.marchand@redhat.com> References: <20230803075038.307012-1-david.marchand@redhat.com> <20230914123615.1705654-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Define some PCI capability constants and use them in existing drivers. Acked-by: Bruce Richardson Reviewed-by: Chenbo Xia Signed-off-by: David Marchand --- Changes since v2: - adjusted virtio drivers after changes in previous patch, --- drivers/bus/pci/linux/pci_vfio.c | 2 +- drivers/crypto/virtio/virtio_pci.c | 14 +++----------- drivers/event/dlb2/pf/dlb2_main.c | 6 ++---- drivers/net/bnx2x/bnx2x.c | 16 ++++++++-------- drivers/net/bnx2x/bnx2x.h | 4 ---- drivers/net/cxgbe/base/adapter.h | 3 +-- drivers/net/gve/gve_ethdev.c | 2 +- drivers/net/gve/gve_ethdev.h | 2 +- drivers/net/hns3/hns3_ethdev_vf.c | 2 +- drivers/net/virtio/virtio_pci.c | 14 +++----------- drivers/vdpa/ifc/base/ifcvf_osdep.h | 4 +++- lib/pci/rte_pci.h | 5 +++++ 12 files changed, 29 insertions(+), 45 deletions(-) diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c index 614ed5d696..bfedbc1bed 100644 --- a/drivers/bus/pci/linux/pci_vfio.c +++ b/drivers/bus/pci/linux/pci_vfio.c @@ -112,7 +112,7 @@ pci_vfio_get_msix_bar(const struct rte_pci_device *dev, { off_t cap_offset; - cap_offset = rte_pci_find_capability(dev, PCI_CAP_ID_MSIX); + cap_offset = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX); if (cap_offset < 0) return -1; diff --git a/drivers/crypto/virtio/virtio_pci.c b/drivers/crypto/virtio/virtio_pci.c index 19afebdcad..8f4c6bddbe 100644 --- a/drivers/crypto/virtio/virtio_pci.c +++ b/drivers/crypto/virtio/virtio_pci.c @@ -14,14 +14,6 @@ #include "virtio_pci.h" #include "virtqueue.h" -/* - * Following macros are derived from linux/pci_regs.h, however, - * we can't simply include that header here, as there is no such - * file for non-Linux platform. - */ -#define PCI_CAP_ID_VNDR 0x09 -#define PCI_CAP_ID_MSIX 0x11 - /* * The remaining space is defined by each driver as the per-driver * configuration space. @@ -356,7 +348,7 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_crypto_hw *hw) * Transitional devices would also have this capability, * that's why we also check if msix is enabled. */ - pos = rte_pci_find_capability(dev, PCI_CAP_ID_MSIX); + pos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX); if (pos > 0 && rte_pci_read_config(dev, &flags, sizeof(flags), pos + 2) == sizeof(flags)) { if (flags & PCI_MSIX_ENABLE) @@ -367,7 +359,7 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_crypto_hw *hw) hw->use_msix = VIRTIO_MSIX_NONE; } - pos = rte_pci_find_capability(dev, PCI_CAP_ID_VNDR); + pos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_VNDR); while (pos > 0) { if (rte_pci_read_config(dev, &cap, sizeof(cap), pos) != sizeof(cap)) break; @@ -396,7 +388,7 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_crypto_hw *hw) break; } - pos = rte_pci_find_next_capability(dev, PCI_CAP_ID_VNDR, pos); + pos = rte_pci_find_next_capability(dev, RTE_PCI_CAP_ID_VNDR, pos); } if (hw->common_cfg == NULL || hw->notify_base == NULL || diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index 40e5cb594f..1a229baee0 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -38,8 +38,6 @@ #define DLB2_PCI_EXP_DEVSTA_TRPND 0x20 #define DLB2_PCI_EXP_DEVCTL_BCR_FLR 0x8000 -#define DLB2_PCI_CAP_ID_EXP 0x10 -#define DLB2_PCI_CAP_ID_MSIX 0x11 #define DLB2_PCI_EXT_CAP_ID_PRI 0x13 #define DLB2_PCI_EXT_CAP_ID_ACS 0xD @@ -244,7 +242,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) return ret; } - pcie_cap_offset = rte_pci_find_capability(pdev, DLB2_PCI_CAP_ID_EXP); + pcie_cap_offset = rte_pci_find_capability(pdev, RTE_PCI_CAP_ID_EXP); if (pcie_cap_offset < 0) { DLB2_LOG_ERR("[%s()] failed to find the pcie capability\n", @@ -483,7 +481,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } - msix_cap_offset = rte_pci_find_capability(pdev, DLB2_PCI_CAP_ID_MSIX); + msix_cap_offset = rte_pci_find_capability(pdev, RTE_PCI_CAP_ID_MSIX); if (msix_cap_offset >= 0) { off = msix_cap_offset + DLB2_PCI_MSIX_FLAGS; if (rte_pci_read_config(pdev, &cmd, 2, off) == 2) { diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c index 06f2949885..8a97de8806 100644 --- a/drivers/net/bnx2x/bnx2x.c +++ b/drivers/net/bnx2x/bnx2x.c @@ -7613,7 +7613,7 @@ static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg) struct bnx2x_pci_cap *caps; /* ensure PCIe capability is enabled */ - caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP); + caps = pci_find_cap(sc, RTE_PCI_CAP_ID_EXP, BNX2X_PCI_CAP); if (NULL != caps) { PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: " "id=0x%04X type=0x%04X addr=0x%08X", @@ -7647,7 +7647,7 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc) int reg = 0; /* check if PCI Power Management is enabled */ - caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP); + caps = pci_find_cap(sc, RTE_PCI_CAP_ID_PM, BNX2X_PCI_CAP); if (NULL != caps) { PMD_DRV_LOG(DEBUG, sc, "Found PM capability: " "id=0x%04X type=0x%04X addr=0x%08X", @@ -7669,7 +7669,7 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc) sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG; /* check if MSI capability is enabled */ - caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP); + caps = pci_find_cap(sc, RTE_PCI_CAP_ID_MSI, BNX2X_PCI_CAP); if (NULL != caps) { PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg); @@ -7678,7 +7678,7 @@ static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc) } /* check if MSI-X capability is enabled */ - caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP); + caps = pci_find_cap(sc, RTE_PCI_CAP_ID_MSIX, BNX2X_PCI_CAP); if (NULL != caps) { PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg); @@ -9587,10 +9587,10 @@ static void bnx2x_init_multi_cos(struct bnx2x_softc *sc) } static uint8_t bnx2x_pci_capabilities[] = { - PCIY_EXPRESS, - PCIY_PMG, - PCIY_MSI, - PCIY_MSIX, + RTE_PCI_CAP_ID_EXP, + RTE_PCI_CAP_ID_PM, + RTE_PCI_CAP_ID_MSI, + RTE_PCI_CAP_ID_MSIX, }; static int bnx2x_pci_get_caps(struct bnx2x_softc *sc) diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index 89414ac88a..07ef0567c2 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -33,10 +33,6 @@ #ifndef RTE_EXEC_ENV_FREEBSD #include -#define PCIY_PMG PCI_CAP_ID_PM -#define PCIY_MSI PCI_CAP_ID_MSI -#define PCIY_EXPRESS PCI_CAP_ID_EXP -#define PCIY_MSIX PCI_CAP_ID_MSIX #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA diff --git a/drivers/net/cxgbe/base/adapter.h b/drivers/net/cxgbe/base/adapter.h index 00d7591ea4..7bee5cf3a8 100644 --- a/drivers/net/cxgbe/base/adapter.h +++ b/drivers/net/cxgbe/base/adapter.h @@ -511,8 +511,7 @@ static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, CXGBE_WRITE_REG64(adapter, reg_addr, val); } -/* Offset of first capability list entry */ -#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ +#define PCI_CAP_ID_EXP RTE_PCI_CAP_ID_EXP #define PCI_EXP_DEVCTL 0x0008 /* Device control */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c index c276b9e68e..9ea5dbaeea 100644 --- a/drivers/net/gve/gve_ethdev.c +++ b/drivers/net/gve/gve_ethdev.c @@ -609,7 +609,7 @@ gve_teardown_device_resources(struct gve_priv *priv) static int pci_dev_msix_vec_count(struct rte_pci_device *pdev) { - off_t msix_pos = rte_pci_find_capability(pdev, PCI_CAP_ID_MSIX); + off_t msix_pos = rte_pci_find_capability(pdev, RTE_PCI_CAP_ID_MSIX); uint16_t control; if (msix_pos > 0 && rte_pci_read_config(pdev, &control, sizeof(control), diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h index 8759b1c76e..d604a75b7f 100644 --- a/drivers/net/gve/gve_ethdev.h +++ b/drivers/net/gve/gve_ethdev.h @@ -8,6 +8,7 @@ #include #include #include +#include #include "base/gve.h" @@ -19,7 +20,6 @@ * we can't simply include that header here, as there is no such * file for non-Linux platform. */ -#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ #define PCI_MSIX_FLAGS 2 /* Message Control */ #define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index b731850b01..eab5c55f5e 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -61,7 +61,7 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op) return 0; } - pos = rte_pci_find_capability(device, PCI_CAP_ID_MSIX); + pos = rte_pci_find_capability(device, RTE_PCI_CAP_ID_MSIX); if (pos > 0) { ret = rte_pci_read_config(device, &control, sizeof(control), pos + PCI_MSIX_FLAGS); diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c index 4c2a1911d1..ffdacecd6d 100644 --- a/drivers/net/virtio/virtio_pci.c +++ b/drivers/net/virtio/virtio_pci.c @@ -15,14 +15,6 @@ #include "virtio_logs.h" #include "virtqueue.h" -/* - * Following macros are derived from linux/pci_regs.h, however, - * we can't simply include that header here, as there is no such - * file for non-Linux platform. - */ -#define PCI_CAP_ID_VNDR 0x09 -#define PCI_CAP_ID_MSIX 0x11 - /* * The remaining space is defined by each driver as the per-driver * configuration space. @@ -40,7 +32,7 @@ vtpci_msix_detect(struct rte_pci_device *dev) uint16_t flags; off_t pos; - pos = rte_pci_find_capability(dev, PCI_CAP_ID_MSIX); + pos = rte_pci_find_capability(dev, RTE_PCI_CAP_ID_MSIX); if (pos > 0 && rte_pci_read_config(dev, &flags, sizeof(flags), pos + 2) == sizeof(flags)) { if (flags & PCI_MSIX_ENABLE) @@ -607,7 +599,7 @@ virtio_read_caps(struct rte_pci_device *pci_dev, struct virtio_hw *hw) */ dev->msix_status = vtpci_msix_detect(pci_dev); - pos = rte_pci_find_capability(pci_dev, PCI_CAP_ID_VNDR); + pos = rte_pci_find_capability(pci_dev, RTE_PCI_CAP_ID_VNDR); while (pos > 0) { if (rte_pci_read_config(pci_dev, &cap, sizeof(cap), pos) != sizeof(cap)) break; @@ -637,7 +629,7 @@ virtio_read_caps(struct rte_pci_device *pci_dev, struct virtio_hw *hw) break; } - pos = rte_pci_find_next_capability(pci_dev, PCI_CAP_ID_VNDR, pos); + pos = rte_pci_find_next_capability(pci_dev, RTE_PCI_CAP_ID_VNDR, pos); } if (dev->common_cfg == NULL || dev->notify_base == NULL || diff --git a/drivers/vdpa/ifc/base/ifcvf_osdep.h b/drivers/vdpa/ifc/base/ifcvf_osdep.h index 6444d7f72c..dd2ff08f77 100644 --- a/drivers/vdpa/ifc/base/ifcvf_osdep.h +++ b/drivers/vdpa/ifc/base/ifcvf_osdep.h @@ -6,7 +6,6 @@ #define _IFCVF_OSDEP_H_ #include -#include #include #include @@ -35,6 +34,9 @@ typedef struct rte_pci_device PCI_DEV; #define PCI_READ_CONFIG_DWORD(dev, val, where) \ rte_pci_read_config(dev, val, 4, where) +#define PCI_CAPABILITY_LIST RTE_PCI_CAPABILITY_LIST +#define PCI_CAP_ID_VNDR RTE_PCI_CAP_ID_VNDR + typedef uint8_t u8; typedef int8_t s8; typedef uint16_t u16; diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index a6a38462cb..8e030caef2 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -44,6 +44,11 @@ extern "C" { #define RTE_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ /* Capability registers (RTE_PCI_CAPABILITY_LIST) */ +#define RTE_PCI_CAP_ID_PM 0x01 /* Power Management */ +#define RTE_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ +#define RTE_PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ +#define RTE_PCI_CAP_ID_EXP 0x10 /* PCI Express */ +#define RTE_PCI_CAP_ID_MSIX 0x11 /* MSI-X */ #define RTE_PCI_CAP_SIZEOF 4 #define RTE_PCI_CAP_NEXT 1 -- 2.41.0