From: Itamar Gozlan <igozlan@nvidia.com>
To: <valex@nvidia.com>, <viacheslavo@nvidia.com>,
<thomas@monjalon.net>, <suanmingm@nvidia.com>,
Matan Azrad <matan@nvidia.com>, Ori Kam <orika@nvidia.com>
Cc: <dev@dpdk.org>
Subject: [PATCH 2/5] net/mlx5/hws: support additional 4 C registers
Date: Mon, 18 Sep 2023 15:07:02 +0300 [thread overview]
Message-ID: <20230918120705.265025-2-igozlan@nvidia.com> (raw)
In-Reply-To: <20230918120705.265025-1-igozlan@nvidia.com>
New connectX devices have 4 additional registers which can be
used by the application. This support will allow matching on
these new registers.
Signed-off-by: Itamar Gozlan <igozlan@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 4 ++++
drivers/net/mlx5/hws/mlx5dr_definer.c | 16 ++++++++++++++++
drivers/net/mlx5/hws/mlx5dr_definer.h | 4 ++++
3 files changed, 24 insertions(+)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 51f426c614..4ead9ba2c7 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -857,6 +857,10 @@ enum modify_reg {
REG_C_5,
REG_C_6,
REG_C_7,
+ REG_C_8,
+ REG_C_9,
+ REG_C_10,
+ REG_C_11,
};
/* Modification sub command. */
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index b82af9d102..2f6f91892b 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -1412,6 +1412,22 @@ mlx5dr_definer_get_register_fc(struct mlx5dr_definer_conv_data *cd, int reg)
fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_7];
DR_CALC_SET_HDR(fc, registers, register_c_7);
break;
+ case REG_C_8:
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_8];
+ DR_CALC_SET_HDR(fc, registers, register_c_8);
+ break;
+ case REG_C_9:
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_9];
+ DR_CALC_SET_HDR(fc, registers, register_c_9);
+ break;
+ case REG_C_10:
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_10];
+ DR_CALC_SET_HDR(fc, registers, register_c_10);
+ break;
+ case REG_C_11:
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_11];
+ DR_CALC_SET_HDR(fc, registers, register_c_11);
+ break;
case REG_A:
fc = &cd->fc[MLX5DR_DEFINER_FNAME_REG_A];
DR_CALC_SET_HDR(fc, metadata, general_purpose);
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index bf026fa6bb..f5a541bc17 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -100,6 +100,10 @@ enum mlx5dr_definer_fname {
MLX5DR_DEFINER_FNAME_REG_5,
MLX5DR_DEFINER_FNAME_REG_6,
MLX5DR_DEFINER_FNAME_REG_7,
+ MLX5DR_DEFINER_FNAME_REG_8,
+ MLX5DR_DEFINER_FNAME_REG_9,
+ MLX5DR_DEFINER_FNAME_REG_10,
+ MLX5DR_DEFINER_FNAME_REG_11,
MLX5DR_DEFINER_FNAME_REG_A,
MLX5DR_DEFINER_FNAME_REG_B,
MLX5DR_DEFINER_FNAME_GRE_KEY_PRESENT,
--
2.38.1
next prev parent reply other threads:[~2023-09-18 12:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-18 12:07 [PATCH 1/5] net/mlx5/hws: add support for matching on bth_a bit Itamar Gozlan
2023-09-18 12:07 ` Itamar Gozlan [this message]
2023-09-18 12:07 ` [PATCH 3/5] net/mlx5/hws: supporting add_field action Itamar Gozlan
2023-09-18 12:07 ` [PATCH 4/5] net/mlx5/hws: supporting default miss table in HWS Itamar Gozlan
2023-10-29 16:02 ` Ori Kam
2023-09-18 12:07 ` [PATCH 5/5] net/mlx5/hws: fix field copy bind Itamar Gozlan
2023-10-09 7:57 ` [PATCH 1/5] net/mlx5/hws: add support for matching on bth_a bit Matan Azrad
2023-10-10 9:33 ` Raslan Darawsheh
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