From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D757E42604; Tue, 19 Sep 2023 15:43:17 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1D2F140DF5; Tue, 19 Sep 2023 15:43:09 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7D0BE40E09 for ; Tue, 19 Sep 2023 15:43:07 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38JDZvGl011923; Tue, 19 Sep 2023 06:43:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=oOdnfywSSqWkdyWkDVlsYIVFNFaueqbNJmlpPKqJeZg=; b=QFpATvB/HoheuK2hwt3Aav3PyY9HWemwCI0Hjmckc63rqp88b+GvSqY7k4x4dwcx8bQm rNYzkvgQT7jLNBOzSn50f116x6g7tEeYqjvpvLg3bRSyrGxBViPUiN/JgGZ3oVwf5e5h pWihwgUoozBI0KFjY/lAy631tvsaGBN6MDdqKRdWXSkIbBDVyGSNBVMJp3k1kHR20ipR Suc1m9DNdsarR+DjLf6bDgAw8oMJmx1wokNEVD2CMm2/Ksx3rzuUP05BfOBiATKgcCCE bK7RPVdU6Xi6FnUcjhnX+6ojZw/wMC7CRJ5WhkCh1byZrkzOoP4uPO3wgYEvN+KXUSQz nw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3t7cnq00wc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 19 Sep 2023 06:43:06 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 19 Sep 2023 06:43:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 19 Sep 2023 06:43:04 -0700 Received: from localhost.localdomain (unknown [10.28.36.157]) by maili.marvell.com (Postfix) with ESMTP id 0CF893F709C; Tue, 19 Sep 2023 06:42:59 -0700 (PDT) From: Amit Prakash Shukla To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Vamsi Attunuru CC: , , , , , , , , , , , , Amit Prakash Shukla Subject: [PATCH v1 5/7] common/cnxk: dma result to an offset of the event Date: Tue, 19 Sep 2023 19:12:20 +0530 Message-ID: <20230919134222.2500033-5-amitprakashs@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919134222.2500033-1-amitprakashs@marvell.com> References: <20230919134222.2500033-1-amitprakashs@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 0GGzNQyGvA4xtvp_MuG4o58UUS_B-nu4 X-Proofpoint-GUID: 0GGzNQyGvA4xtvp_MuG4o58UUS_B-nu4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-19_06,2023-09-19_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds support to configure writing result to offset of the DMA response event. Signed-off-by: Amit Prakash Shukla --- drivers/common/cnxk/roc_dpi.c | 5 ++++- drivers/common/cnxk/roc_dpi.h | 2 +- drivers/common/cnxk/roc_dpi_priv.h | 4 ++++ drivers/common/cnxk/roc_idev.c | 20 ++++++++++++++++++++ drivers/common/cnxk/roc_idev_priv.h | 3 +++ drivers/dma/cnxk/cnxk_dmadev.c | 3 ++- drivers/dma/cnxk/cnxk_dmadev.h | 1 + 7 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_dpi.c b/drivers/common/cnxk/roc_dpi.c index 2e086b3698..7bf6ac2aaf 100644 --- a/drivers/common/cnxk/roc_dpi.c +++ b/drivers/common/cnxk/roc_dpi.c @@ -84,6 +84,8 @@ roc_dpi_configure(struct roc_dpi *roc_dpi, uint32_t chunk_sz, uint64_t aura, uin mbox_msg.s.aura = aura; mbox_msg.s.sso_pf_func = idev_sso_pffunc_get(); mbox_msg.s.npa_pf_func = idev_npa_pffunc_get(); + mbox_msg.s.wqecs = 1; + mbox_msg.s.wqecsoff = idev_dma_cs_offset_get(); rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg, sizeof(dpi_mbox_msg_t)); @@ -95,7 +97,7 @@ roc_dpi_configure(struct roc_dpi *roc_dpi, uint32_t chunk_sz, uint64_t aura, uin } int -roc_dpi_dev_init(struct roc_dpi *roc_dpi) +roc_dpi_dev_init(struct roc_dpi *roc_dpi, uint8_t offset) { struct plt_pci_device *pci_dev = roc_dpi->pci_dev; uint16_t vfid; @@ -104,6 +106,7 @@ roc_dpi_dev_init(struct roc_dpi *roc_dpi) vfid = ((pci_dev->addr.devid & 0x1F) << 3) | (pci_dev->addr.function & 0x7); vfid -= 1; roc_dpi->vfid = vfid; + idev_dma_cs_offset_set(offset); return 0; } diff --git a/drivers/common/cnxk/roc_dpi.h b/drivers/common/cnxk/roc_dpi.h index 4ebde5b8a6..978e2badb2 100644 --- a/drivers/common/cnxk/roc_dpi.h +++ b/drivers/common/cnxk/roc_dpi.h @@ -11,7 +11,7 @@ struct roc_dpi { uint16_t vfid; } __plt_cache_aligned; -int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi); +int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi, uint8_t offset); int __roc_api roc_dpi_dev_fini(struct roc_dpi *roc_dpi); int __roc_api roc_dpi_configure(struct roc_dpi *dpi, uint32_t chunk_sz, uint64_t aura, diff --git a/drivers/common/cnxk/roc_dpi_priv.h b/drivers/common/cnxk/roc_dpi_priv.h index 518a3e7351..52962c8bc0 100644 --- a/drivers/common/cnxk/roc_dpi_priv.h +++ b/drivers/common/cnxk/roc_dpi_priv.h @@ -31,6 +31,10 @@ typedef union dpi_mbox_msg_t { uint64_t sso_pf_func : 16; /* NPA PF function */ uint64_t npa_pf_func : 16; + /* WQE queue DMA completion status enable */ + uint64_t wqecs : 1; + /* WQE queue DMA completion status offset */ + uint64_t wqecsoff : 8; } s; } dpi_mbox_msg_t; diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c index e6c6b34d78..7b922c8bae 100644 --- a/drivers/common/cnxk/roc_idev.c +++ b/drivers/common/cnxk/roc_idev.c @@ -301,6 +301,26 @@ idev_sso_set(struct roc_sso *sso) __atomic_store_n(&idev->sso, sso, __ATOMIC_RELEASE); } +void +idev_dma_cs_offset_set(uint8_t offset) +{ + struct idev_cfg *idev = idev_get_cfg(); + + if (idev != NULL) + idev->dma_cs_offset = offset; +} + +uint8_t +idev_dma_cs_offset_get(void) +{ + struct idev_cfg *idev = idev_get_cfg(); + + if (idev != NULL) + return idev->dma_cs_offset; + + return 0; +} + uint64_t roc_idev_nix_inl_meta_aura_get(void) { diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h index 80f8465e1c..cf63c58d92 100644 --- a/drivers/common/cnxk/roc_idev_priv.h +++ b/drivers/common/cnxk/roc_idev_priv.h @@ -37,6 +37,7 @@ struct idev_cfg { struct roc_nix_list roc_nix_list; plt_spinlock_t nix_inl_dev_lock; plt_spinlock_t npa_dev_lock; + uint8_t dma_cs_offset; }; /* Generic */ @@ -55,6 +56,8 @@ void idev_sso_pffunc_set(uint16_t sso_pf_func); uint16_t idev_sso_pffunc_get(void); struct roc_sso *idev_sso_get(void); void idev_sso_set(struct roc_sso *sso); +void idev_dma_cs_offset_set(uint8_t offset); +uint8_t idev_dma_cs_offset_get(void); /* idev lmt */ uint16_t idev_lmt_pffunc_get(void); diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c index 26680edfde..db127e056f 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.c +++ b/drivers/dma/cnxk/cnxk_dmadev.c @@ -511,6 +511,7 @@ static const struct rte_dma_dev_ops cnxk_dmadev_ops = { static int cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) { + struct cnxk_dpi_compl_s *compl = NULL; struct cnxk_dpi_vf_s *dpivf = NULL; char name[RTE_DEV_NAME_MAX_LEN]; struct rte_dma_dev *dmadev; @@ -556,7 +557,7 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_de rdpi = &dpivf->rdpi; rdpi->pci_dev = pci_dev; - rc = roc_dpi_dev_init(rdpi); + rc = roc_dpi_dev_init(rdpi, (uint64_t)&compl->wqecs); if (rc < 0) goto err_out_free; diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h index 350ae73b5c..75059b8843 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.h +++ b/drivers/dma/cnxk/cnxk_dmadev.h @@ -86,6 +86,7 @@ union cnxk_dpi_instr_cmd { struct cnxk_dpi_compl_s { uint64_t cdata; void *cb_data; + uint32_t wqecs; }; struct cnxk_dpi_cdesc_data_s { -- 2.25.1