From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C62AD42672; Fri, 29 Sep 2023 15:48:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D594840DDC; Fri, 29 Sep 2023 15:48:57 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3B3B940A6F for ; Fri, 29 Sep 2023 15:48:56 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38TCQPik006219 for ; Fri, 29 Sep 2023 06:48:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=BN2/4bNvU5YUdI7hsru4N1U0OI2HIrGOyRsDQDRWgQ4=; b=cxk2OJtrCDgXtkYBwTLPC1vKF4pINVgrNpSDw7lvlLb6kK+qGfuyiCikVjQXI956eBs+ ztzLiwM+ERUX3444Oj1bswuT5bzK5ZMnQNyXzqWUc/8Nq/BRxacaoR+kY+GG/4HyeHOw H/8TDFFaxdfqI8tFYM3QEMnUd5hZSPMk5kR9LyV+XXJxHQz+yUHMLr/ThAQefmrIKWb7 mGVcwUzgwBYErMGSDB6F9ZZf9+99Weloh/XCuirU9gCT/JGf+w84cCdBRF7uD27vSIPe lAHr0OclPNgwwzi2GiDTWuAu+uZHsjhKjW41fo8WwIcCukgmx3jwbhy+trK+5yVmE5zC Dg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tdxk08fkq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 29 Sep 2023 06:48:54 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 29 Sep 2023 06:48:53 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 29 Sep 2023 06:48:53 -0700 Received: from localhost.localdomain (unknown [10.28.36.157]) by maili.marvell.com (Postfix) with ESMTP id C36165B6923; Fri, 29 Sep 2023 06:48:51 -0700 (PDT) From: Amit Prakash Shukla To: Vamsi Attunuru CC: , , Amit Prakash Shukla Subject: [PATCH] doc: add cnxk dmadev performance tuning details Date: Fri, 29 Sep 2023 19:18:46 +0530 Message-ID: <20230929134846.625979-1-amitprakashs@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: UMaDZdIW7b62oeG8RuFeP8zF-s6pSpuD X-Proofpoint-ORIG-GUID: UMaDZdIW7b62oeG8RuFeP8zF-s6pSpuD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-29_11,2023-09-28_03,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Updated cnxk DMA driver document to explain about performance tuning parameters for kernel module. Signed-off-by: Amit Prakash Shukla --- doc/guides/dmadevs/cnxk.rst | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/doc/guides/dmadevs/cnxk.rst b/doc/guides/dmadevs/cnxk.rst index 418b9a9d63..8d841b1f12 100644 --- a/doc/guides/dmadevs/cnxk.rst +++ b/doc/guides/dmadevs/cnxk.rst @@ -56,3 +56,33 @@ Performing Data Copies Refer to the :ref:`Enqueue / Dequeue APIs ` section of the dmadev library documentation for details on operation enqueue and submission API usage. + +Performance Tuning Parameters +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To achieve higher performance, DMA device needs to be tuned using PF kernel driver +module params. The PF kernel driver is part of the octeon sdk. Module params shall be +configured during module insert as in below example:: + + $ sudo insmod octeontx2_dpi.ko mps=128 mrrs=128 eng_fifo_buf=0x101008080808 + +* ``mps`` + Maximum payload size. MPS size shall not exceed the size selected by PCI config. + Max size that shall be configured can be found on executing ``lspci`` command + for the device. + +* ``mrrs`` + Maximum read request size. MRRS size shall not exceed the size selected by PCI + config. Max size that shall be configured can be found on executing ``lspci`` + command for the device. + +* ``eng_fifo_buf`` + CNXK supports 6 DMA engines and each engine has an associated FIFO. By-default + all engine's FIFO is configured to 8 KB. Engine FIFO size can be tuned using this + 64 bit variable, where each byte represents an engine. In the example above engine + 0-3 FIFO are configure as 8 KB and engine 4-5 are configured as 16 KB. + +.. note:: + MPS and MRRS performance tuning parameters helps achieve higher performance + only for Inbound and Outbound DMA transfers. The parameter has no effect for + Internal only DMA transfer. -- 2.25.1