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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by MWH0EPF000971E6.mail.protection.outlook.com (10.167.243.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.19 via Frontend Transport; Tue, 31 Oct 2023 14:28:31 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 31 Oct 2023 07:28:11 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 31 Oct 2023 07:28:09 -0700 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko , Ori Kam , Suanming Mou CC: , Raslan Darawsheh , Bing Zhao Subject: [PATCH 8/8] net/mlx5: add support for vport match selection Date: Tue, 31 Oct 2023 16:27:33 +0200 Message-ID: <20231031142733.2009166-9-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231031142733.2009166-1-dsosnowski@nvidia.com> References: <20231031142733.2009166-1-dsosnowski@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E6:EE_|CH0PR12MB8551:EE_ X-MS-Office365-Filtering-Correlation-Id: f8225162-1a4b-4818-118b-08dbda1da81d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CAT:NONE; SFS:(13230031)(4636009)(376002)(346002)(136003)(396003)(39860400002)(230173577357003)(230273577357003)(230922051799003)(64100799003)(1800799009)(82310400011)(186009)(451199024)(36840700001)(46966006)(40470700004)(478600001)(7696005)(110136005)(6666004)(70206006)(70586007)(336012)(426003)(16526019)(6286002)(26005)(1076003)(107886003)(41300700001)(2616005)(2906002)(86362001)(5660300002)(54906003)(6636002)(4326008)(8676002)(8936002)(316002)(82740400003)(36756003)(36860700001)(83380400001)(47076005)(356005)(7636003)(40480700001)(40460700003)(55016003)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2023 14:28:31.0878 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8225162-1a4b-4818-118b-08dbda1da81d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8551 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Bing Zhao A new devarg "vport_match" is introduced for the application to use. If set to 1, then matching using REPRESENTED_PORT items on group 0 will be forced to use "misc.source_port", instead of matching on the vport metadata in HWS mode. It allows the user to match on the traffic from E-Switch manager. A new devarg "vport_match" is introduced for the application to use. This enables the force matching on "misc.source_port" for item REPRESENTED_PORT on group 0, instead of matching on the metadata REG_C_0 bits in HWS mode. It will allow the user to match on the traffic from E-Switch manager. By default, this is set to 0. When enable it with 1, the default FDB jump rule should be disabled by set "fdb_def_rule_en=0". Signed-off-by: Bing Zhao Acked-by: Viacheslav Ovsiienko --- doc/guides/nics/mlx5.rst | 16 ++++++++++++++++ drivers/net/mlx5/mlx5.c | 17 +++++++++++++++++ drivers/net/mlx5/mlx5.h | 2 ++ drivers/net/mlx5/mlx5_flow_dv.c | 2 +- drivers/net/mlx5/mlx5_trigger.c | 5 ++++- 5 files changed, 40 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 584f592433..8c65f16db8 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1369,6 +1369,22 @@ for an additional list of options shared with other mlx5 drivers. By default, the PMD will set this value to 1. +- ``vport_match`` parameter [int] + + Controls the underlying matching mechanism for REPRESENTED_PORT items when they are used for + flow rules in E-Switch root flow table. + + If set to 1, then ``source_vport`` matching is used. This allows applications to match whole + traffic coming from the application by using REPRESENTED_PORT item with ``port_id == UINT16_MAX``. + As a side effect, flow rules in root flow table will not be able match physical ports explicitly, + when running on Multiport E-Switch. + Matching in non-root flow tables (group bigger than 1) is not affected. + + If set to 0, then ``vport_metadata`` matching is used. This is the default mechanism. + + By default, the PMD will set this value to 0. Setting ``vport_match`` to 1 requires that + ``fdb_def_rule_en`` is set to 0, so that E-Switch root flow table is exposed to the application. + Sub-Function ------------ diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index f929d6547c..c275cdfee8 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -184,6 +184,9 @@ /* Device parameter to control representor matching in ingress/egress flows with HWS. */ #define MLX5_REPR_MATCHING_EN "repr_matching_en" +/* Representor matching field selection: 0 - meta_vport, 1 - misc.vport */ +#define MLX5_HWS_ROOT_VPORT_MATCH "vport_match" + /* Shared memory between primary and secondary processes. */ struct mlx5_shared_data *mlx5_shared_data; @@ -1425,6 +1428,8 @@ mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque) config->cnt_svc.cycle_time = tmp; } else if (strcmp(MLX5_REPR_MATCHING_EN, key) == 0) { config->repr_matching = !!tmp; + } else if (strcmp(MLX5_HWS_ROOT_VPORT_MATCH, key) == 0) { + config->vport_match = !!tmp; } return 0; } @@ -1464,6 +1469,7 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh, MLX5_HWS_CNT_SERVICE_CORE, MLX5_HWS_CNT_CYCLE_TIME, MLX5_REPR_MATCHING_EN, + MLX5_HWS_ROOT_VPORT_MATCH, NULL, }; int ret = 0; @@ -1522,6 +1528,11 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh, rte_errno = ENODEV; return -rte_errno; } + if (config->dv_flow_en == 2 && config->fdb_def_rule && config->vport_match) { + DRV_LOG(DEBUG, "vport_match=1 is incompatible with FDB default rule " + "(fdb_def_rule-en=1). Setting vport_match=0."); + config->vport_match = 0; + } if (!config->tx_pp && config->tx_skew && !sh->cdev->config.hca_attr.wait_on_time) { DRV_LOG(WARNING, @@ -1562,6 +1573,7 @@ mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh, config->allow_duplicate_pattern); DRV_LOG(DEBUG, "\"fdb_def_rule_en\" is %u.", config->fdb_def_rule); DRV_LOG(DEBUG, "\"repr_matching_en\" is %u.", config->repr_matching); + DRV_LOG(DEBUG, "\"vport_match\" is %u.", config->vport_match); return 0; } @@ -3003,6 +3015,11 @@ mlx5_probe_again_args_validate(struct mlx5_common_device *cdev, sh->ibdev_name); goto error; } + if (sh->config.vport_match ^ config->vport_match) { + DRV_LOG(ERR, "\"vport_match\" configuration mismatch for shared %s context.", + sh->ibdev_name); + goto error; + } mlx5_free(config); return 0; error: diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 484c5eb3df..5299b1321a 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -352,6 +352,7 @@ struct mlx5_sh_config { /* Allow/Prevent the duplicate rules pattern. */ uint32_t fdb_def_rule:1; /* Create FDB default jump rule */ uint32_t repr_matching:1; /* Enable implicit vport matching in HWS FDB. */ + uint32_t vport_match:1; /* Root table representor matching field selection. */ }; /* Structure for VF VLAN workaround. */ @@ -1782,6 +1783,7 @@ struct mlx5_priv { uint32_t mark_enabled:1; /* If mark action is enabled on rxqs. */ uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ uint32_t tunnel_enabled:1; /* If tunnel offloading is enabled on rxqs. */ + uint32_t vport_match:1; /* vport match field. */ uint16_t domain_id; /* Switch domain identifier. */ uint16_t vport_id; /* Associated VF vport index (if any). */ uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index a39b4600e6..5b5716692c 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -10594,7 +10594,7 @@ flow_dv_translate_item_represented_port(struct rte_eth_dev *dev, void *key, * Kernel can use either misc.source_port or half of C0 metadata * register. */ - if (priv->vport_meta_mask) { + if (priv->vport_meta_mask && !priv->vport_match) { /* * Provide the hint for SW steering library * to insert the flow into ingress domain and diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 7bdb897612..d28cbe1dfd 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1515,7 +1515,10 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) goto error; } } else { - DRV_LOG(INFO, "port %u FDB default rule is disabled", dev->data->port_id); + DRV_LOG(INFO, "port %u FDB default rule is disabled with vport_match %u", + dev->data->port_id, config->vport_match); + /* vport_match is only interesting in no default FDB rule mode. */ + priv->vport_match = config->vport_match; } if (priv->isolated) return 0; -- 2.25.1