From: Simon Ellmann <simon.ellmann@tum.de>
To: qiming.yang@intel.com, wenjun1.wu@intel.com
Cc: dev@dpdk.org, Simon Ellmann <simon.ellmann@tum.de>
Subject: [PATCH] ixgbe: fix interrupt clear mask for eimc register
Date: Fri, 8 Dec 2023 16:44:10 +0100 [thread overview]
Message-ID: <20231208154410.14212-1-simon.ellmann@tum.de> (raw)
32nd bit of the eimc register is reserved according to the datasheet
Signed-off-by: Simon Ellmann <simon.ellmann@tum.de>
---
drivers/net/ixgbe/base/ixgbe_type.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h
index 1094df5891..03b299cd10 100644
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -2023,7 +2023,7 @@ enum {
#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
/* Interrupt clear mask */
-#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
+#define IXGBE_IRQ_CLEAR_MASK 0x7FFFFFFF
/* Interrupt Vector Allocation Registers */
#define IXGBE_IVAR_REG_NUM 25
--
2.43.0
next reply other threads:[~2023-12-08 15:49 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-08 15:44 Simon Ellmann [this message]
2023-12-14 2:24 ` Zhang, Qi Z
2023-12-14 11:02 ` Simon Ellmann
2023-12-19 3:32 ` Zhang, Qi Z
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