From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EBF78436BE; Sun, 10 Dec 2023 02:32:40 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0671140DFD; Sun, 10 Dec 2023 02:31:54 +0100 (CET) Received: from mail-ot1-f50.google.com (mail-ot1-f50.google.com [209.85.210.50]) by mails.dpdk.org (Postfix) with ESMTP id BEF0440693 for ; Sun, 10 Dec 2023 02:31:50 +0100 (CET) Received: by mail-ot1-f50.google.com with SMTP id 46e09a7af769-6d9f7af8918so1050804a34.0 for ; Sat, 09 Dec 2023 17:31:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1702171909; x=1702776709; darn=dpdk.org; h=mime-version:references:in-reply-to:message-id:date:subject:to:from :from:to:cc:subject:date:message-id:reply-to; bh=9OS7ghr+tS0GSRV50CNPSzhMHmIzfZ1U5pb49Hcqzw8=; b=beZLI/sq/4BYL84wpQhF5w8bYJ0SalSUCmzvp9zNJtJa6KG7ytLjNxjWxgsVd1fQ05 lRwGHtK206Ofnf0Pf4y7Jg5ESkkImKFMwgMb46U+zhJJD4P43Qr5FMKylyzp415LnES6 BfqoGuNH3qoRbfJG8DBkLsThUQJNAUEIsYGSo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702171909; x=1702776709; h=mime-version:references:in-reply-to:message-id:date:subject:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=9OS7ghr+tS0GSRV50CNPSzhMHmIzfZ1U5pb49Hcqzw8=; b=w5HQDKZRrzyLzz2OT+//WOO73q8fdgVEVYojyDcQAZrT4tGP8s02EUYXCpxp8SOQh2 8uWs999dl6s5VE/WaWY1ObMkLK81GrMInLfjM+XsUJzv2fOdMvzVBJgdoaZ6C2e6J0ji w0lDjY4spylChQRSNnx8BGtkQ0UpYePefW0bgPTm7QiinNa+EKpVN+K1A2PpLOdvp9La FXZsbp3B3h+YreKYt2au/LeE0iN5jwFLw/haYdgxFlW8bdO17xWvoTuIYw3rhWCwGcPe SFOdo4xFmkO45ZUFhBtUbV2H9UYXzjQ7Ud1iW6FuIuHc09GAknFkw16CmyYXwo6jpeS8 PooA== X-Gm-Message-State: AOJu0YyaGaXqFvcFhO26W3YivQsvKSH0Yzas6MtVZkDJJLl1URuiMBfO IMACZPxFTfhdWZ48VkBEwMTrM45dx30q0OJlW0sSuhf7n4+nGrC7tRJ6ivhyEQ1Txr4/TSkIW23 FGeTXycaTKwuPZ2UChqKxcUmJEoaeV7btuLsALUH1LseSneMWCRZb8gAQwBoRbC+lWg7M X-Google-Smtp-Source: AGHT+IHhyl63zkRQVE+/PNPCJoDUQ8ffGe/5snzLOpVvtxUCGsIaivRGSMcx/39fRkjWx1THXHYObw== X-Received: by 2002:a05:6359:420a:b0:170:17eb:377b with SMTP id kn10-20020a056359420a00b0017017eb377bmr3077544rwb.35.1702171909296; Sat, 09 Dec 2023 17:31:49 -0800 (PST) Received: from localhost.localdomain ([2605:a601:a780:1400:6d20:fff:e413:282a]) by smtp.gmail.com with ESMTPSA id q3-20020a170902f78300b001d083fed5f3sm4006050pln.60.2023.12.09.17.31.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Dec 2023 17:31:48 -0800 (PST) From: Ajit Khaparde To: dev@dpdk.org Subject: [PATCH v2 07/14] net/bnxt: refactor code to support P7 devices Date: Sat, 9 Dec 2023 17:24:48 -0800 Message-Id: <20231210012455.20229-8-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20231210012455.20229-1-ajit.khaparde@broadcom.com> References: <20231210012455.20229-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="00000000000008ec0a060c1dc890" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org --00000000000008ec0a060c1dc890 Content-Transfer-Encoding: 8bit Refactor code to support the P7 device family. The changes include support for RSS, VNIC allocation, TPA. Remove unnecessary check to disable vector mode support for some device families. Signed-off-by: Ajit Khaparde --- drivers/net/bnxt/bnxt.h | 6 +++--- drivers/net/bnxt/bnxt_ethdev.c | 27 ++++++++------------------- drivers/net/bnxt/bnxt_flow.c | 2 +- drivers/net/bnxt/bnxt_hwrm.c | 26 ++++++++++++++------------ drivers/net/bnxt/bnxt_ring.c | 6 +++--- drivers/net/bnxt/bnxt_rxq.c | 2 +- drivers/net/bnxt/bnxt_rxr.c | 6 +++--- drivers/net/bnxt/bnxt_vnic.c | 6 +++--- 8 files changed, 36 insertions(+), 45 deletions(-) diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index 3a1d8a6ff6..7439ecf4fa 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -107,11 +107,11 @@ #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */ #define BNXT_TPA_MAX_AGGS(bp) \ - (BNXT_CHIP_P5(bp) ? TPA_MAX_AGGS_TH : \ + (BNXT_CHIP_P5_P7(bp) ? TPA_MAX_AGGS_TH : \ TPA_MAX_AGGS) #define BNXT_TPA_MAX_SEGS(bp) \ - (BNXT_CHIP_P5(bp) ? TPA_MAX_SEGS_TH : \ + (BNXT_CHIP_P5_P7(bp) ? TPA_MAX_SEGS_TH : \ TPA_MAX_SEGS) /* @@ -938,7 +938,7 @@ inline uint16_t bnxt_max_rings(struct bnxt *bp) * RSS table size in P5 is 512. * Cap max Rx rings to the same value for RSS. */ - if (BNXT_CHIP_P5(bp)) + if (BNXT_CHIP_P5_P7(bp)) max_rx_rings = RTE_MIN(max_rx_rings, BNXT_RSS_TBL_SIZE_P5); max_tx_rings = RTE_MIN(max_tx_rings, max_rx_rings); diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 1e4182071a..2a41fafa02 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -212,7 +212,7 @@ uint16_t bnxt_rss_ctxts(const struct bnxt *bp) unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5); - if (!BNXT_CHIP_P5(bp)) + if (!BNXT_CHIP_P5_P7(bp)) return 1; return RTE_ALIGN_MUL_CEIL(num_rss_rings, @@ -222,7 +222,7 @@ uint16_t bnxt_rss_ctxts(const struct bnxt *bp) uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) { - if (!BNXT_CHIP_P5(bp)) + if (!BNXT_CHIP_P5_P7(bp)) return HW_HASH_INDEX_SIZE; return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5; @@ -765,7 +765,7 @@ static int bnxt_start_nic(struct bnxt *bp) /* P5 does not support ring groups. * But we will use the array to save RSS context IDs. */ - if (BNXT_CHIP_P5(bp)) + if (BNXT_CHIP_P5_P7(bp)) bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; rc = bnxt_vnic_queue_db_init(bp); @@ -1247,12 +1247,6 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev) { struct bnxt *bp = eth_dev->data->dev_private; - /* Disable vector mode RX for Stingray2 for now */ - if (BNXT_CHIP_SR2(bp)) { - bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; - return bnxt_recv_pkts; - } - #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) /* Vector mode receive cannot be enabled if scattered rx is in use. */ if (eth_dev->data->scattered_rx) @@ -1319,14 +1313,9 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev) static eth_tx_burst_t bnxt_transmit_function(struct rte_eth_dev *eth_dev) { - struct bnxt *bp = eth_dev->data->dev_private; - - /* Disable vector mode TX for Stingray2 for now */ - if (BNXT_CHIP_SR2(bp)) - return bnxt_xmit_pkts; - #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; + struct bnxt *bp = eth_dev->data->dev_private; /* * Vector mode transmit can be enabled only if not using scatter rx @@ -2091,7 +2080,7 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, continue; rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); - if (BNXT_CHIP_P5(bp)) { + if (BNXT_CHIP_P5_P7(bp)) { vnic->rss_table[i * 2] = rxq->rx_ring->rx_ring_struct->fw_ring_id; vnic->rss_table[i * 2 + 1] = @@ -2138,7 +2127,7 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, if (reta_conf[idx].mask & (1ULL << sft)) { uint16_t qid; - if (BNXT_CHIP_P5(bp)) + if (BNXT_CHIP_P5_P7(bp)) qid = bnxt_rss_to_qid(bp, vnic->rss_table[i * 2]); else @@ -3224,7 +3213,7 @@ bnxt_rx_queue_count_op(void *rx_queue) break; case CMPL_BASE_TYPE_RX_TPA_END: - if (BNXT_CHIP_P5(rxq->bp)) { + if (BNXT_CHIP_P5_P7(rxq->bp)) { struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; p5_tpa_end = (void *)rxcmp; @@ -3335,7 +3324,7 @@ bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) if (desc == offset) return RTE_ETH_RX_DESC_DONE; - if (BNXT_CHIP_P5(rxq->bp)) { + if (BNXT_CHIP_P5_P7(rxq->bp)) { struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; p5_tpa_end = (void *)rxcmp; diff --git a/drivers/net/bnxt/bnxt_flow.c b/drivers/net/bnxt/bnxt_flow.c index 28dd5ae6cb..15f0e1b308 100644 --- a/drivers/net/bnxt/bnxt_flow.c +++ b/drivers/net/bnxt/bnxt_flow.c @@ -1199,7 +1199,7 @@ bnxt_vnic_rss_cfg_update(struct bnxt *bp, if (i == bp->rx_cp_nr_rings) return 0; - if (BNXT_CHIP_P5(bp)) { + if (BNXT_CHIP_P5_P7(bp)) { rxq = bp->rx_queues[idx]; vnic->rss_table[rss_idx * 2] = rxq->rx_ring->rx_ring_struct->fw_ring_id; diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index fe9e629892..2d0a7a2731 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -853,7 +853,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id); bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows); bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs); - if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs) + if (!BNXT_CHIP_P5_P7(bp) && !bp->pdev->max_vfs) bp->max_l2_ctx += bp->max_rx_em_flows; if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) bp->max_vnics = rte_le_to_cpu_16(BNXT_MAX_VNICS_COS_CLASSIFY); @@ -1187,7 +1187,7 @@ int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp) * So use the value provided by func_qcaps. */ bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs); - if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs) + if (!BNXT_CHIP_P5_P7(bp) && !bp->pdev->max_vfs) bp->max_l2_ctx += bp->max_rx_em_flows; if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) bp->max_vnics = rte_le_to_cpu_16(BNXT_MAX_VNICS_COS_CLASSIFY); @@ -1744,7 +1744,7 @@ int bnxt_hwrm_ring_alloc(struct bnxt *bp, req.ring_type = ring_type; req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id); req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id); - if (BNXT_CHIP_P5(bp)) { + if (BNXT_CHIP_P5_P7(bp)) { mb_pool = bp->rx_queues[0]->mb_pool; rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) - RTE_PKTMBUF_HEADROOM; @@ -2118,7 +2118,7 @@ int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic) HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB); - if (BNXT_CHIP_P5(bp)) { + if (BNXT_CHIP_P5_P7(bp)) { int dflt_rxq = vnic->start_grp_id; struct bnxt_rx_ring_info *rxr; struct bnxt_cp_ring_info *cpr; @@ -2304,7 +2304,7 @@ int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic) { int rc = 0; - if (BNXT_CHIP_P5(bp)) { + if (BNXT_CHIP_P5_P7(bp)) { int j; for (j = 0; j < vnic->num_lb_ctxts; j++) { @@ -2556,7 +2556,7 @@ int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp, struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 }; struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr; - if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) { + if ((BNXT_CHIP_P5(bp) || BNXT_CHIP_P7(bp)) && !bp->max_tpa_v2) { if (enable) PMD_DRV_LOG(ERR, "No HW support for LRO\n"); return -ENOTSUP; @@ -2584,6 +2584,9 @@ int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp, req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp)); req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp)); req.min_agg_len = rte_cpu_to_le_32(512); + + if (BNXT_CHIP_P5_P7(bp)) + req.max_aggs = rte_cpu_to_le_16(bp->max_tpa_v2); } req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id); @@ -2836,7 +2839,7 @@ void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index) ring = rxr ? rxr->ag_ring_struct : NULL; if (ring != NULL && cpr != NULL) { bnxt_hwrm_ring_free(bp, ring, - BNXT_CHIP_P5(bp) ? + BNXT_CHIP_P5_P7(bp) ? HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG : HWRM_RING_FREE_INPUT_RING_TYPE_RX, cpr->cp_ring_struct->fw_ring_id); @@ -3356,8 +3359,7 @@ int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up) /* Get user requested autoneg setting */ autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds); - - if (BNXT_CHIP_P5(bp) && + if (BNXT_CHIP_P5_P7(bp) && dev_conf->link_speeds & RTE_ETH_LINK_SPEED_40G) { /* 40G is not supported as part of media auto detect. * The speed should be forced and autoneg disabled @@ -5348,7 +5350,7 @@ int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic) if (!(vnic->rss_table && vnic->hash_type)) return 0; - if (BNXT_CHIP_P5(bp)) + if (BNXT_CHIP_P5_P7(bp)) return bnxt_vnic_rss_configure_p5(bp, vnic); /* @@ -5440,7 +5442,7 @@ int bnxt_hwrm_set_ring_coal(struct bnxt *bp, int rc; /* Set ring coalesce parameters only for 100G NICs */ - if (BNXT_CHIP_P5(bp)) { + if (BNXT_CHIP_P5_P7(bp)) { if (bnxt_hwrm_set_coal_params_p5(bp, &req)) return -1; } else if (bnxt_stratus_device(bp)) { @@ -5470,7 +5472,7 @@ int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp) int total_alloc_len; int rc, i, tqm_rings; - if (!BNXT_CHIP_P5(bp) || + if (!BNXT_CHIP_P5_P7(bp) || bp->hwrm_spec_code < HWRM_VERSION_1_9_2 || BNXT_VF(bp) || bp->ctx) diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c index 6dacb1b37f..90cad6c9c6 100644 --- a/drivers/net/bnxt/bnxt_ring.c +++ b/drivers/net/bnxt/bnxt_ring.c @@ -57,7 +57,7 @@ int bnxt_alloc_ring_grps(struct bnxt *bp) /* P5 does not support ring groups. * But we will use the array to save RSS context IDs. */ - if (BNXT_CHIP_P5(bp)) { + if (BNXT_CHIP_P5_P7(bp)) { bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) { /* 1 ring is for default completion ring */ @@ -354,7 +354,7 @@ static void bnxt_set_db(struct bnxt *bp, uint32_t fid, uint32_t ring_mask) { - if (BNXT_CHIP_P5(bp)) { + if (BNXT_CHIP_P5_P7(bp)) { int db_offset = DB_PF_OFFSET; switch (ring_type) { case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX: @@ -559,7 +559,7 @@ static int bnxt_alloc_rx_agg_ring(struct bnxt *bp, int queue_index) ring->fw_rx_ring_id = rxr->rx_ring_struct->fw_ring_id; - if (BNXT_CHIP_P5(bp)) { + if (BNXT_CHIP_P5_P7(bp)) { ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG; hw_stats_ctx_id = cpr->hw_stats_ctx_id; } else { diff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c index 0d0b5e28e4..575e7f193f 100644 --- a/drivers/net/bnxt/bnxt_rxq.c +++ b/drivers/net/bnxt/bnxt_rxq.c @@ -600,7 +600,7 @@ int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) if (bp->rx_queues[i]->rx_started) active_queue_cnt++; - if (BNXT_CHIP_P5(bp)) { + if (BNXT_CHIP_P5_P7(bp)) { /* * For P5, we need to ensure that the VNIC default * receive ring corresponds to an active receive queue. diff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c index 0cabfb583c..9d45065f28 100644 --- a/drivers/net/bnxt/bnxt_rxr.c +++ b/drivers/net/bnxt/bnxt_rxr.c @@ -334,7 +334,7 @@ static int bnxt_rx_pages(struct bnxt_rx_queue *rxq, uint16_t cp_cons, ag_cons; struct rx_pkt_cmpl *rxcmp; struct rte_mbuf *last = mbuf; - bool is_p5_tpa = tpa_info && BNXT_CHIP_P5(rxq->bp); + bool is_p5_tpa = tpa_info && BNXT_CHIP_P5_P7(rxq->bp); for (i = 0; i < agg_buf; i++) { struct rte_mbuf **ag_buf; @@ -395,7 +395,7 @@ static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, } else if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) { struct rx_tpa_end_cmpl *tpa_end = cmp; - if (BNXT_CHIP_P5(bp)) + if (BNXT_CHIP_P5_P7(bp)) return 0; agg_bufs = BNXT_TPA_END_AGG_BUFS(tpa_end); @@ -430,7 +430,7 @@ static inline struct rte_mbuf *bnxt_tpa_end( return NULL; } - if (BNXT_CHIP_P5(rxq->bp)) { + if (BNXT_CHIP_P5_P7(rxq->bp)) { struct rx_tpa_v2_end_cmpl *th_tpa_end; struct rx_tpa_v2_end_cmpl_hi *th_tpa_end1; diff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c index d40daf631e..bf93120d28 100644 --- a/drivers/net/bnxt/bnxt_vnic.c +++ b/drivers/net/bnxt/bnxt_vnic.c @@ -143,7 +143,7 @@ int bnxt_alloc_vnic_attributes(struct bnxt *bp, bool reconfig) entry_length = HW_HASH_KEY_SIZE; - if (BNXT_CHIP_P5(bp)) + if (BNXT_CHIP_P5_P7(bp)) rss_table_size = BNXT_RSS_TBL_SIZE_P5 * 2 * sizeof(*vnic->rss_table); else @@ -418,8 +418,8 @@ static int32_t bnxt_vnic_populate_rss_table(struct bnxt *bp, struct bnxt_vnic_info *vnic) { - /* RSS table population is different for p4 and p5 platforms */ - if (BNXT_CHIP_P5(bp)) + /* RSS table population is different for p4 and p5, p7 platforms */ + if (BNXT_CHIP_P5_P7(bp)) return bnxt_vnic_populate_rss_table_p5(bp, vnic); return bnxt_vnic_populate_rss_table_p4(bp, vnic); -- 2.39.2 (Apple Git-143) --00000000000008ec0a060c1dc890 Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIIQdgYJKoZIhvcNAQcCoIIQZzCCEGMCAQExDzANBglghkgBZQMEAgEFADALBgkqhkiG9w0BBwGg gg3NMIIFDTCCA/WgAwIBAgIQeEqpED+lv77edQixNJMdADANBgkqhkiG9w0BAQsFADBMMSAwHgYD VQQLExdHbG9iYWxTaWduIFJvb3QgQ0EgLSBSMzETMBEGA1UEChMKR2xvYmFsU2lnbjETMBEGA1UE AxMKR2xvYmFsU2lnbjAeFw0yMDA5MTYwMDAwMDBaFw0yODA5MTYwMDAwMDBaMFsxCzAJBgNVBAYT AkJFMRkwFwYDVQQKExBHbG9iYWxTaWduIG52LXNhMTEwLwYDVQQDEyhHbG9iYWxTaWduIEdDQyBS MyBQZXJzb25hbFNpZ24gMiBDQSAyMDIwMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA vbCmXCcsbZ/a0fRIQMBxp4gJnnyeneFYpEtNydrZZ+GeKSMdHiDgXD1UnRSIudKo+moQ6YlCOu4t rVWO/EiXfYnK7zeop26ry1RpKtogB7/O115zultAz64ydQYLe+a1e/czkALg3sgTcOOcFZTXk38e aqsXsipoX1vsNurqPtnC27TWsA7pk4uKXscFjkeUE8JZu9BDKaswZygxBOPBQBwrA5+20Wxlk6k1 e6EKaaNaNZUy30q3ArEf30ZDpXyfCtiXnupjSK8WU2cK4qsEtj09JS4+mhi0CTCrCnXAzum3tgcH cHRg0prcSzzEUDQWoFxyuqwiwhHu3sPQNmFOMwIDAQABo4IB2jCCAdYwDgYDVR0PAQH/BAQDAgGG MGAGA1UdJQRZMFcGCCsGAQUFBwMCBggrBgEFBQcDBAYKKwYBBAGCNxQCAgYKKwYBBAGCNwoDBAYJ KwYBBAGCNxUGBgorBgEEAYI3CgMMBggrBgEFBQcDBwYIKwYBBQUHAxEwEgYDVR0TAQH/BAgwBgEB /wIBADAdBgNVHQ4EFgQUljPR5lgXWzR1ioFWZNW+SN6hj88wHwYDVR0jBBgwFoAUj/BLf6guRSSu TVD6Y5qL3uLdG7wwegYIKwYBBQUHAQEEbjBsMC0GCCsGAQUFBzABhiFodHRwOi8vb2NzcC5nbG9i YWxzaWduLmNvbS9yb290cjMwOwYIKwYBBQUHMAKGL2h0dHA6Ly9zZWN1cmUuZ2xvYmFsc2lnbi5j b20vY2FjZXJ0L3Jvb3QtcjMuY3J0MDYGA1UdHwQvMC0wK6ApoCeGJWh0dHA6Ly9jcmwuZ2xvYmFs c2lnbi5jb20vcm9vdC1yMy5jcmwwWgYDVR0gBFMwUTALBgkrBgEEAaAyASgwQgYKKwYBBAGgMgEo CjA0MDIGCCsGAQUFBwIBFiZodHRwczovL3d3dy5nbG9iYWxzaWduLmNvbS9yZXBvc2l0b3J5LzAN BgkqhkiG9w0BAQsFAAOCAQEAdAXk/XCnDeAOd9nNEUvWPxblOQ/5o/q6OIeTYvoEvUUi2qHUOtbf jBGdTptFsXXe4RgjVF9b6DuizgYfy+cILmvi5hfk3Iq8MAZsgtW+A/otQsJvK2wRatLE61RbzkX8 9/OXEZ1zT7t/q2RiJqzpvV8NChxIj+P7WTtepPm9AIj0Keue+gS2qvzAZAY34ZZeRHgA7g5O4TPJ /oTd+4rgiU++wLDlcZYd/slFkaT3xg4qWDepEMjT4T1qFOQIL+ijUArYS4owpPg9NISTKa1qqKWJ jFoyms0d0GwOniIIbBvhI2MJ7BSY9MYtWVT5jJO3tsVHwj4cp92CSFuGwunFMzCCA18wggJHoAMC AQICCwQAAAAAASFYUwiiMA0GCSqGSIb3DQEBCwUAMEwxIDAeBgNVBAsTF0dsb2JhbFNpZ24gUm9v dCBDQSAtIFIzMRMwEQYDVQQKEwpHbG9iYWxTaWduMRMwEQYDVQQDEwpHbG9iYWxTaWduMB4XDTA5 MDMxODEwMDAwMFoXDTI5MDMxODEwMDAwMFowTDEgMB4GA1UECxMXR2xvYmFsU2lnbiBSb290IENB IC0gUjMxEzARBgNVBAoTCkdsb2JhbFNpZ24xEzARBgNVBAMTCkdsb2JhbFNpZ24wggEiMA0GCSqG SIb3DQEBAQUAA4IBDwAwggEKAoIBAQDMJXaQeQZ4Ihb1wIO2hMoonv0FdhHFrYhy/EYCQ8eyip0E XyTLLkvhYIJG4VKrDIFHcGzdZNHr9SyjD4I9DCuul9e2FIYQebs7E4B3jAjhSdJqYi8fXvqWaN+J J5U4nwbXPsnLJlkNc96wyOkmDoMVxu9bi9IEYMpJpij2aTv2y8gokeWdimFXN6x0FNx04Druci8u nPvQu7/1PQDhBjPogiuuU6Y6FnOM3UEOIDrAtKeh6bJPkC4yYOlXy7kEkmho5TgmYHWyn3f/kRTv riBJ/K1AFUjRAjFhGV64l++td7dkmnq/X8ET75ti+w1s4FRpFqkD2m7pg5NxdsZphYIXAgMBAAGj QjBAMA4GA1UdDwEB/wQEAwIBBjAPBgNVHRMBAf8EBTADAQH/MB0GA1UdDgQWBBSP8Et/qC5FJK5N UPpjmove4t0bvDANBgkqhkiG9w0BAQsFAAOCAQEAS0DbwFCq/sgM7/eWVEVJu5YACUGssxOGhigH M8pr5nS5ugAtrqQK0/Xx8Q+Kv3NnSoPHRHt44K9ubG8DKY4zOUXDjuS5V2yq/BKW7FPGLeQkbLmU Y/vcU2hnVj6DuM81IcPJaP7O2sJTqsyQiunwXUaMld16WCgaLx3ezQA3QY/tRG3XUyiXfvNnBB4V 14qWtNPeTCekTBtzc3b0F5nCH3oO4y0IrQocLP88q1UOD5F+NuvDV0m+4S4tfGCLw0FREyOdzvcy a5QBqJnnLDMfOjsl0oZAzjsshnjJYS8Uuu7bVW/fhO4FCU29KNhyztNiUGUe65KXgzHZs7XKR1g/ XzCCBVUwggQ9oAMCAQICDAzZWuPidkrRZaiw2zANBgkqhkiG9w0BAQsFADBbMQswCQYDVQQGEwJC RTEZMBcGA1UEChMQR2xvYmFsU2lnbiBudi1zYTExMC8GA1UEAxMoR2xvYmFsU2lnbiBHQ0MgUjMg UGVyc29uYWxTaWduIDIgQ0EgMjAyMDAeFw0yMjA5MTAwODE4NDVaFw0yNTA5MTAwODE4NDVaMIGW MQswCQYDVQQGEwJJTjESMBAGA1UECBMJS2FybmF0YWthMRIwEAYDVQQHEwlCYW5nYWxvcmUxFjAU BgNVBAoTDUJyb2FkY29tIEluYy4xHDAaBgNVBAMTE0FqaXQgS3VtYXIgS2hhcGFyZGUxKTAnBgkq hkiG9w0BCQEWGmFqaXQua2hhcGFyZGVAYnJvYWRjb20uY29tMIIBIjANBgkqhkiG9w0BAQEFAAOC AQ8AMIIBCgKCAQEArZ/Aqg34lMOo2BabvAa+dRThl9OeUUJMob125dz+jvS78k4NZn1mYrHu53Dn YycqjtuSMlJ6vJuwN2W6QpgTaA2SDt5xTB7CwA2urpcm7vWxxLOszkr5cxMB1QBbTd77bXFuyTqW jrer3VIWqOujJ1n+n+1SigMwEr7PKQR64YKq2aRYn74ukY3DlQdKUrm2yUkcA7aExLcAwHWUna/u pZEyqKnwS1lKCzjX7mV5W955rFsFxChdAKfw0HilwtqdY24mhy62+GeaEkD0gYIj1tCmw9gnQToc K+0s7xEunfR9pBrzmOwS3OQbcP0nJ8SmQ8R+reroH6LYuFpaqK1rgQIDAQABo4IB2zCCAdcwDgYD VR0PAQH/BAQDAgWgMIGjBggrBgEFBQcBAQSBljCBkzBOBggrBgEFBQcwAoZCaHR0cDovL3NlY3Vy ZS5nbG9iYWxzaWduLmNvbS9jYWNlcnQvZ3NnY2NyM3BlcnNvbmFsc2lnbjJjYTIwMjAuY3J0MEEG CCsGAQUFBzABhjVodHRwOi8vb2NzcC5nbG9iYWxzaWduLmNvbS9nc2djY3IzcGVyc29uYWxzaWdu MmNhMjAyMDBNBgNVHSAERjBEMEIGCisGAQQBoDIBKAowNDAyBggrBgEFBQcCARYmaHR0cHM6Ly93 d3cuZ2xvYmFsc2lnbi5jb20vcmVwb3NpdG9yeS8wCQYDVR0TBAIwADBJBgNVHR8EQjBAMD6gPKA6 hjhodHRwOi8vY3JsLmdsb2JhbHNpZ24uY29tL2dzZ2NjcjNwZXJzb25hbHNpZ24yY2EyMDIwLmNy bDAlBgNVHREEHjAcgRphaml0LmtoYXBhcmRlQGJyb2FkY29tLmNvbTATBgNVHSUEDDAKBggrBgEF BQcDBDAfBgNVHSMEGDAWgBSWM9HmWBdbNHWKgVZk1b5I3qGPzzAdBgNVHQ4EFgQUbrcTuh0mr2qP xYdtyDgFeRIiE/gwDQYJKoZIhvcNAQELBQADggEBALrc1TljKrDhXicOaZlzIQyqOEkKAZ324i8X OwzA0n2EcPGmMZvgARurvanSLD3mLeeuyq1feCcjfGM1CJFh4+EY7EkbFbpVPOIdstSBhbnAJnOl aC/q0wTndKoC/xXBhXOZB8YL/Zq4ZclQLMUO6xi/fFRyHviI5/IrosdrpniXFJ9ukJoOXtvdrEF+ KlMYg/Deg9xo3wddCqQIsztHSkR4XaANdn+dbLRQpctZ13BY1lim4uz5bYn3M0IxyZWkQ1JuPHCK aRJv0SfR88PoI4RB7NCEHqFwARTj1KvFPQi8pK/YISFydZYbZrxQdyWDidqm4wSuJfpE6i0cWvCd u50xggJtMIICaQIBATBrMFsxCzAJBgNVBAYTAkJFMRkwFwYDVQQKExBHbG9iYWxTaWduIG52LXNh MTEwLwYDVQQDEyhHbG9iYWxTaWduIEdDQyBSMyBQZXJzb25hbFNpZ24gMiBDQSAyMDIwAgwM2Vrj 4nZK0WWosNswDQYJYIZIAWUDBAIBBQCggdQwLwYJKoZIhvcNAQkEMSIEIHrdx1gbQvSThIJhesYc 2AJP3XPm7jcXYacufe7NK07IMBgGCSqGSIb3DQEJAzELBgkqhkiG9w0BBwEwHAYJKoZIhvcNAQkF MQ8XDTIzMTIxMDAxMzE0OVowaQYJKoZIhvcNAQkPMVwwWjALBglghkgBZQMEASowCwYJYIZIAWUD BAEWMAsGCWCGSAFlAwQBAjAKBggqhkiG9w0DBzALBgkqhkiG9w0BAQowCwYJKoZIhvcNAQEHMAsG CWCGSAFlAwQCATANBgkqhkiG9w0BAQEFAASCAQAsOdi0IKzLQUVUIuPVRCEyGwRWfNVtQZ+Sdwep 6wwKzBU1K6no8/aVYs5oALcZoYjQvu2yJvlQklz91obuwH4JBQ+l/hKfgfdtVPSANPZXQ4Go8ZMQ rYHBNHJffChTZ+khhhM+tizS/aBvpzHoyT/xzG85nWZHPdzTfjEMmuK1n50xkYXiOc4avSAGjJzB gloLjNQ+47SmvAJyqH8pIMUEQqpKYu+/n5VoegkuaBWcY+9oGkwYgg1qmOs8KmhJHx8wQIVKrNXL wQqgZLWc9am9jwSzLfFSWx9XeOgTQNRyONTBzCBMYt/hd0JQCHpiee9TiWbwdwYg2fx5cXH7DKln --00000000000008ec0a060c1dc890--