* [PATCH 1/2] common/qat: add vqat definition to pmd map @ 2023-12-18 13:41 Arkadiusz Kusztal 2023-12-18 13:41 ` [PATCH 2/2] common/qat: add vqat confiuration macros Arkadiusz Kusztal 2024-02-18 22:25 ` [PATCH v2] common/qat: add symmetric crypto virtual qat device (vQAT) Arkadiusz Kusztal 0 siblings, 2 replies; 12+ messages in thread From: Arkadiusz Kusztal @ 2023-12-18 13:41 UTC (permalink / raw) To: dev; +Cc: gakhil, kai.ji, ciara.power, Arkadiusz Kusztal This commit adds vqat (virtual QAT device) to PMD PCI ID map. Signed-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com> --- drivers/common/qat/qat_common.h | 1 + drivers/common/qat/qat_device.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h index 9411a79301..53799ce174 100644 --- a/drivers/common/qat/qat_common.h +++ b/drivers/common/qat/qat_common.h @@ -21,6 +21,7 @@ enum qat_device_gen { QAT_GEN2, QAT_GEN3, QAT_GEN4, + QAT_VQAT, QAT_N_GENS }; diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c index f55dc3c6f0..5e00c200a6 100644 --- a/drivers/common/qat/qat_device.c +++ b/drivers/common/qat/qat_device.c @@ -199,6 +199,8 @@ pick_gen(const struct rte_pci_device *pci_dev) case 0x4943: case 0x4945: return QAT_GEN4; + case 0x0da5: + return QAT_VQAT; default: QAT_LOG(ERR, "Invalid dev_id, can't determine generation"); return QAT_N_GENS; -- 2.13.6 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/2] common/qat: add vqat confiuration macros 2023-12-18 13:41 [PATCH 1/2] common/qat: add vqat definition to pmd map Arkadiusz Kusztal @ 2023-12-18 13:41 ` Arkadiusz Kusztal 2024-02-18 22:25 ` [PATCH v2] common/qat: add symmetric crypto virtual qat device (vQAT) Arkadiusz Kusztal 1 sibling, 0 replies; 12+ messages in thread From: Arkadiusz Kusztal @ 2023-12-18 13:41 UTC (permalink / raw) To: dev; +Cc: gakhil, kai.ji, ciara.power, Arkadiusz Kusztal This commit adds vqat (virtual QAT device) configuration macros to the Intel QuickAssist Technology PMD. Signed-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com> --- .../qat/qat_adf/adf_transport_access_macros_vqat.h | 82 ++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h b/drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h new file mode 100644 index 0000000000..9acf7c614d --- /dev/null +++ b/drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) + * Copyright(c) 2023 Intel Corporation + */ + +#ifndef ADF_TRANSPORT_ACCESS_MACROS_VQAT_H +#define ADF_TRANSPORT_ACCESS_MACROS_VQAT_H + +#define ADF_RINGS_PER_INT_SRCSEL_VQAT 2 +#define ADF_BANK_INT_SRC_SEL_MASK_VQAT 0x44UL +#define ADF_BANK_INT_FLAG_CLEAR_MASK_VQAT 0x3 +#define ADF_RING_BUNDLE_SIZE_VQAT 0x2000 +#define ADF_RING_CSR_ADDR_OFFSET_VQAT 0x0 +#define ADF_RING_CSR_RING_CONFIG_VQAT ADF_VQAT_R0_CONFIG +#define ADF_RING_CSR_RING_LBASE_VQAT ADF_VQAT_R0_LBASE +#define ADF_RING_CSR_RING_UBASE_VQAT ADF_VQAT_R0_UBASE +#define ADF_RING_CSR_RP_IDX_TX 0 +#define ADF_RING_CSR_RP_IDX_RX 1 + +#define BUILD_RING_BASE_ADDR_VQAT(addr, size) \ + ((((addr) >> 6) & (0xFFFFFFFFFFFFFFFFULL << (size))) << 6) +#define READ_CSR_RING_HEAD_VQAT(csr_base_addr, bank, ring) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_RING_HEAD + ((ring) << 2)) +#define READ_CSR_RING_TAIL_VQAT(csr_base_addr, bank, ring) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_RING_TAIL + ((ring) << 2)) +#define READ_CSR_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_STAT) +#define READ_CSR_UO_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_UO_STAT) +#define READ_CSR_E_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_E_STAT) +#define READ_CSR_NE_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_NE_STAT) +#define READ_CSR_NF_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_NF_STAT) +#define READ_CSR_F_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_F_STAT) +#define READ_CSR_C_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_C_STAT) +#define READ_CSR_RING_CONFIG_VQAT(csr_base_addr, bank, ring) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_RING_CONFIG_VQAT + ((ring) << 2)) +#define WRITE_CSR_RING_CONFIG_VQAT(csr_base_addr, bank, ring, value) \ + ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_RING_CONFIG_VQAT + ((ring) << 2), (value)) +#define WRITE_CSR_RING_BASE_VQAT(csr_base_addr, bank, ring, value) \ +do { \ + void __iomem *_csr_base_addr = csr_base_addr; \ + u32 _bank = bank; \ + u32 _ring = ring; \ + dma_addr_t _value = value; \ + u32 l_base = 0, u_base = 0; \ + l_base = (u32)((_value) & 0xFFFFFFFF); \ + u_base = (u32)(((_value) & 0xFFFFFFFF00000000ULL) >> 32); \ + ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (_bank)) + \ + ADF_RING_CSR_RING_LBASE_VQAT + ((_ring) << 2), l_base); \ + ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (_bank)) + \ + ADF_RING_CSR_RING_UBASE_VQAT + ((_ring) << 2), u_base); \ +} while (0) + +#endif -- 2.13.6 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2] common/qat: add symmetric crypto virtual qat device (vQAT) 2023-12-18 13:41 [PATCH 1/2] common/qat: add vqat definition to pmd map Arkadiusz Kusztal 2023-12-18 13:41 ` [PATCH 2/2] common/qat: add vqat confiuration macros Arkadiusz Kusztal @ 2024-02-18 22:25 ` Arkadiusz Kusztal 2024-02-21 7:50 ` [PATCH v3] common/qat: add " Arkadiusz Kusztal 1 sibling, 1 reply; 12+ messages in thread From: Arkadiusz Kusztal @ 2024-02-18 22:25 UTC (permalink / raw) To: dev; +Cc: gakhil, ciara.power, Arkadiusz Kusztal This commit adds virtual QAT device to the Intel QuickAssist Technology PMD. Only symmetric crypto service is enabled with this commit. Signed-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com> --- doc/guides/rel_notes/release_24_03.rst | 3 ++ drivers/common/qat/dev/qat_dev_gen4.c | 39 +++++++++++++++++++- drivers/common/qat/qat_common.h | 1 + drivers/common/qat/qat_device.c | 5 +++ drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 12 ++++-- drivers/crypto/qat/qat_sym_session.c | 13 ++++--- 6 files changed, 62 insertions(+), 11 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index e9c9717706..3b3977a0b6 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -55,6 +55,9 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Updated Intel QuickAssist Technology driver.** + + * Enabled support for virtual QAT - vQAT (0da5) devices in QAT symmetric crypto driver. Removed Items ------------- diff --git a/drivers/common/qat/dev/qat_dev_gen4.c b/drivers/common/qat/dev/qat_dev_gen4.c index 1ce262f715..8f59fa2d31 100644 --- a/drivers/common/qat/dev/qat_dev_gen4.c +++ b/drivers/common/qat/dev/qat_dev_gen4.c @@ -143,6 +143,26 @@ qat_dev_read_config_gen4(struct qat_pci_device *qat_dev) return 0; } +static int +qat_dev_read_config_vqat(struct qat_pci_device *qat_dev) +{ + int i = 0; + struct qat_dev_gen4_extra *dev_extra = qat_dev->dev_private; + struct qat_qp_hw_data *hw_data; + + for (; i < QAT_GEN4_BUNDLE_NUM; i++) { + hw_data = &dev_extra->qp_gen4_data[i][0]; + memset(hw_data, 0, sizeof(*hw_data)); + hw_data->service_type = QAT_SERVICE_SYMMETRIC; + hw_data->tx_msg_size = 128; + hw_data->rx_msg_size = 32; + hw_data->tx_ring_num = 0; + hw_data->rx_ring_num = 1; + hw_data->hw_bundle_num = i; + } + return 0; +} + static void qat_qp_build_ring_base_gen4(void *io_addr, struct qat_queue *queue) @@ -268,6 +288,12 @@ qat_reset_ring_pairs_gen4(struct qat_pci_device *qat_pci_dev) return 0; } +static int +qat_reset_ring_pairs_vqat(struct qat_pci_device *qat_pci_dev __rte_unused) +{ + return 0; +} + static const struct rte_mem_resource * qat_dev_get_transport_bar_gen4(struct rte_pci_device *pci_dev) { @@ -304,10 +330,21 @@ static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen4 = { .qat_dev_get_slice_map = qat_dev_get_slice_map_gen4, }; +static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_vqat = { + .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_vqat, + .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen4, + .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen4, + .qat_dev_read_config = qat_dev_read_config_vqat, + .qat_dev_get_extra_size = qat_dev_get_extra_size_gen4, + .qat_dev_get_slice_map = qat_dev_get_slice_map_gen4, +}; + RTE_INIT(qat_dev_gen_4_init) { - qat_qp_hw_spec[QAT_GEN4] = &qat_qp_hw_spec_gen4; + qat_qp_hw_spec[QAT_VQAT] = qat_qp_hw_spec[QAT_GEN4] = &qat_qp_hw_spec_gen4; qat_dev_hw_spec[QAT_GEN4] = &qat_dev_hw_spec_gen4; + qat_dev_hw_spec[QAT_VQAT] = &qat_dev_hw_spec_vqat; qat_gen_config[QAT_GEN4].dev_gen = QAT_GEN4; + qat_gen_config[QAT_VQAT].dev_gen = QAT_VQAT; qat_gen_config[QAT_GEN4].pf2vf_dev = &qat_pf2vf_gen4; } diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h index 9411a79301..53799ce174 100644 --- a/drivers/common/qat/qat_common.h +++ b/drivers/common/qat/qat_common.h @@ -21,6 +21,7 @@ enum qat_device_gen { QAT_GEN2, QAT_GEN3, QAT_GEN4, + QAT_VQAT, QAT_N_GENS }; diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c index f55dc3c6f0..afcf2b5e99 100644 --- a/drivers/common/qat/qat_device.c +++ b/drivers/common/qat/qat_device.c @@ -62,6 +62,9 @@ static const struct rte_pci_id pci_id_qat_map[] = { { RTE_PCI_DEVICE(0x8086, 0x4945), }, + { + RTE_PCI_DEVICE(0x8086, 0x0da5), + }, {.device_id = 0}, }; @@ -199,6 +202,8 @@ pick_gen(const struct rte_pci_device *pci_dev) case 0x4943: case 0x4945: return QAT_GEN4; + case 0x0da5: + return QAT_VQAT; default: QAT_LOG(ERR, "Invalid dev_id, can't determine generation"); return QAT_N_GENS; diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c index de72383d4b..5798594b4c 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c @@ -406,14 +406,18 @@ qat_sym_configure_raw_dp_ctx_gen4(void *_raw_dp_ctx, void *_ctx) RTE_INIT(qat_sym_crypto_gen4_init) { - qat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1; - qat_sym_gen_dev_ops[QAT_GEN4].get_capabilities = + qat_sym_gen_dev_ops[QAT_VQAT].cryptodev_ops = + qat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1; + qat_sym_gen_dev_ops[QAT_VQAT].get_capabilities = + qat_sym_gen_dev_ops[QAT_GEN4].get_capabilities = qat_sym_crypto_cap_get_gen4; - qat_sym_gen_dev_ops[QAT_GEN4].set_session = + qat_sym_gen_dev_ops[QAT_VQAT].set_session = + qat_sym_gen_dev_ops[QAT_GEN4].set_session = qat_sym_crypto_set_session_gen4; qat_sym_gen_dev_ops[QAT_GEN4].set_raw_dp_ctx = qat_sym_configure_raw_dp_ctx_gen4; - qat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags = + qat_sym_gen_dev_ops[QAT_VQAT].get_feature_flags = + qat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags = qat_sym_crypto_feature_flags_get_gen1; qat_sym_gen_dev_ops[QAT_GEN4].create_security_ctx = qat_sym_create_security_gen1; diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index 9f4f6c3d93..1df990b596 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -405,7 +405,7 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev, goto error_out; } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; break; case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: @@ -911,7 +911,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, session->auth_iv.length = AES_GCM_J0_LEN; else session->is_iv12B = 1; - if (qat_dev_gen == QAT_GEN4) { + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) { session->is_cnt_zero = 1; session->is_ucs = 1; } @@ -1039,7 +1039,7 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev, session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; if (session->cipher_iv.length == 0) { session->cipher_iv.length = AES_GCM_J0_LEN; @@ -1059,13 +1059,13 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev, } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; break; case RTE_CRYPTO_AEAD_CHACHA20_POLY1305: if (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ) return -EINVAL; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305; @@ -2298,7 +2298,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc, auth_param->u2.inner_prefix_sz = qat_hash_get_block_size(cdesc->qat_hash_alg); auth_param->hash_state_sz = digestsize; - if (qat_dev_gen == QAT_GEN4) { + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) { ICP_QAT_FW_HASH_FLAG_MODE2_SET( hash_cd_ctrl->hash_flags, QAT_FW_LA_MODE2); @@ -2840,6 +2840,7 @@ qat_sym_cd_crc_set(struct qat_sym_session *cdesc, cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_gen3_crc_cd); break; case QAT_GEN4: + case QAT_VQAT: crc_cfg.mode = ICP_QAT_HW_CIPHER_ECB_MODE; crc_cfg.algo = ICP_QAT_HW_CIPHER_ALGO_NULL; crc_cfg.hash_cmp_val = 0; -- 2.34.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3] common/qat: add virtual qat device (vQAT) 2024-02-18 22:25 ` [PATCH v2] common/qat: add symmetric crypto virtual qat device (vQAT) Arkadiusz Kusztal @ 2024-02-21 7:50 ` Arkadiusz Kusztal 2024-02-22 12:20 ` Power, Ciara 2024-02-29 10:21 ` [PATCH v4] " Arkadiusz Kusztal 0 siblings, 2 replies; 12+ messages in thread From: Arkadiusz Kusztal @ 2024-02-21 7:50 UTC (permalink / raw) To: dev; +Cc: gakhil, ciara.power, Arkadiusz Kusztal This commit adds virtual QAT device to the Intel QuickAssist Technology PMD. There are three kinds of virtual QAT device defined which offer different QAT service to the customers: symmetric crypto, asymmetric crypto and compression. Signed-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com> --- v2: - added symmetric crypto qp config v3: - added compression - added asymmetric crypto doc/guides/rel_notes/release_24_03.rst | 3 ++ drivers/common/qat/dev/qat_dev_gen4.c | 55 +++++++++++++++++++- drivers/common/qat/qat_adf/icp_qat_hw.h | 5 ++ drivers/common/qat/qat_common.h | 1 + drivers/common/qat/qat_device.c | 7 ++- drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 18 ++++--- drivers/compress/qat/qat_comp_pmd.c | 7 +++ drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 24 ++++++--- drivers/crypto/qat/qat_asym.c | 7 +++ drivers/crypto/qat/qat_sym.c | 7 +++ drivers/crypto/qat/qat_sym_session.c | 13 ++--- 11 files changed, 125 insertions(+), 22 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index e9c9717706..2dc4e7fbd9 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -55,6 +55,9 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Updated Intel QuickAssist Technology driver.** + + * Enabled support for virtual QAT - vQAT (0da5) devices in QAT PMD. Removed Items ------------- diff --git a/drivers/common/qat/dev/qat_dev_gen4.c b/drivers/common/qat/dev/qat_dev_gen4.c index 1ce262f715..1c5a2f2b6f 100644 --- a/drivers/common/qat/dev/qat_dev_gen4.c +++ b/drivers/common/qat/dev/qat_dev_gen4.c @@ -143,6 +143,42 @@ qat_dev_read_config_gen4(struct qat_pci_device *qat_dev) return 0; } +static int +qat_dev_read_config_vqat(struct qat_pci_device *qat_dev) +{ + int i = 0; + struct qat_dev_gen4_extra *dev_extra = qat_dev->dev_private; + struct qat_qp_hw_data *hw_data; + struct qat_device_info *qat_dev_instance = + &qat_pci_devs[qat_dev->qat_dev_id]; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; + + for (; i < QAT_GEN4_BUNDLE_NUM; i++) { + hw_data = &dev_extra->qp_gen4_data[i][0]; + memset(hw_data, 0, sizeof(*hw_data)); + if (sub_id == ADF_VQAT_SYM_PCI_SUBSYSTEM_ID) { + hw_data->service_type = QAT_SERVICE_SYMMETRIC; + hw_data->tx_msg_size = 128; + hw_data->rx_msg_size = 32; + } else if (sub_id == ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID) { + hw_data->service_type = QAT_SERVICE_ASYMMETRIC; + hw_data->tx_msg_size = 64; + hw_data->rx_msg_size = 32; + } else if (sub_id == ADF_VQAT_DC_PCI_SUBSYSTEM_ID) { + hw_data->service_type = QAT_SERVICE_COMPRESSION; + hw_data->tx_msg_size = 128; + hw_data->rx_msg_size = 32; + } else { + QAT_LOG(ERR, "Unrecognized subsystem id %hu", sub_id); + return -EINVAL; + } + hw_data->tx_ring_num = 0; + hw_data->rx_ring_num = 1; + hw_data->hw_bundle_num = i; + } + return 0; +} + static void qat_qp_build_ring_base_gen4(void *io_addr, struct qat_queue *queue) @@ -268,6 +304,12 @@ qat_reset_ring_pairs_gen4(struct qat_pci_device *qat_pci_dev) return 0; } +static int +qat_reset_ring_pairs_vqat(struct qat_pci_device *qat_pci_dev __rte_unused) +{ + return 0; +} + static const struct rte_mem_resource * qat_dev_get_transport_bar_gen4(struct rte_pci_device *pci_dev) { @@ -304,10 +346,21 @@ static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen4 = { .qat_dev_get_slice_map = qat_dev_get_slice_map_gen4, }; +static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_vqat = { + .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_vqat, + .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen4, + .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen4, + .qat_dev_read_config = qat_dev_read_config_vqat, + .qat_dev_get_extra_size = qat_dev_get_extra_size_gen4, + .qat_dev_get_slice_map = qat_dev_get_slice_map_gen4, +}; + RTE_INIT(qat_dev_gen_4_init) { - qat_qp_hw_spec[QAT_GEN4] = &qat_qp_hw_spec_gen4; + qat_qp_hw_spec[QAT_VQAT] = qat_qp_hw_spec[QAT_GEN4] = &qat_qp_hw_spec_gen4; qat_dev_hw_spec[QAT_GEN4] = &qat_dev_hw_spec_gen4; + qat_dev_hw_spec[QAT_VQAT] = &qat_dev_hw_spec_vqat; qat_gen_config[QAT_GEN4].dev_gen = QAT_GEN4; + qat_gen_config[QAT_VQAT].dev_gen = QAT_VQAT; qat_gen_config[QAT_GEN4].pf2vf_dev = &qat_pf2vf_gen4; } diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h index 8b864e1630..638a31ed22 100644 --- a/drivers/common/qat/qat_adf/icp_qat_hw.h +++ b/drivers/common/qat/qat_adf/icp_qat_hw.h @@ -9,6 +9,11 @@ #define ADF_C4XXXIOV_VFLEGFUSES_OFFSET 0x4C #define ADF1_C4XXXIOV_VFLEGFUSES_LEN 4 +/* Definition of virtual QAT subsystem ID*/ +#define ADF_VQAT_SYM_PCI_SUBSYSTEM_ID 0x00 +#define ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID 0x01 +#define ADF_VQAT_DC_PCI_SUBSYSTEM_ID 0x02 + enum icp_qat_slice_mask { ICP_ACCEL_MASK_CIPHER_SLICE = 0x01, ICP_ACCEL_MASK_AUTH_SLICE = 0x02, diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h index 9411a79301..53799ce174 100644 --- a/drivers/common/qat/qat_common.h +++ b/drivers/common/qat/qat_common.h @@ -21,6 +21,7 @@ enum qat_device_gen { QAT_GEN2, QAT_GEN3, QAT_GEN4, + QAT_VQAT, QAT_N_GENS }; diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c index f55dc3c6f0..a9ea4af5df 100644 --- a/drivers/common/qat/qat_device.c +++ b/drivers/common/qat/qat_device.c @@ -62,6 +62,9 @@ static const struct rte_pci_id pci_id_qat_map[] = { { RTE_PCI_DEVICE(0x8086, 0x4945), }, + { + RTE_PCI_DEVICE(0x8086, 0x0da5), + }, {.device_id = 0}, }; @@ -199,6 +202,8 @@ pick_gen(const struct rte_pci_device *pci_dev) case 0x4943: case 0x4945: return QAT_GEN4; + case 0x0da5: + return QAT_VQAT; default: QAT_LOG(ERR, "Invalid dev_id, can't determine generation"); return QAT_N_GENS; @@ -281,6 +286,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev, strlcpy(qat_dev->name, name, QAT_DEV_NAME_MAX_LEN); qat_dev->qat_dev_id = qat_dev_id; qat_dev->qat_dev_gen = qat_dev_gen; + qat_pci_devs[qat_dev_id].pci_dev = pci_dev; ops_hw = qat_dev_hw_spec[qat_dev->qat_dev_gen]; NOT_NULL(ops_hw->qat_dev_get_misc_bar, goto error, @@ -326,7 +332,6 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev, * qat_dev to list of devices */ qat_pci_devs[qat_dev_id].mz = qat_dev_mz; - qat_pci_devs[qat_dev_id].pci_dev = pci_dev; qat_nb_pci_devices++; QAT_LOG(DEBUG, "QAT device %d found, name %s, total QATs %d", diff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c index 05906f13e0..d3de73a02f 100644 --- a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c +++ b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c @@ -198,16 +198,22 @@ qat_comp_get_num_im_bufs_required_gen4(void) RTE_INIT(qat_comp_pmd_gen4_init) { - qat_comp_gen_dev_ops[QAT_GEN4].compressdev_ops = + qat_comp_gen_dev_ops[QAT_VQAT].compressdev_ops = + qat_comp_gen_dev_ops[QAT_GEN4].compressdev_ops = &qat_comp_ops_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_capabilities = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_capabilities = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_capabilities = qat_comp_cap_get_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_num_im_bufs_required = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_num_im_bufs_required = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_num_im_bufs_required = qat_comp_get_num_im_bufs_required_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_ram_bank_flags = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_ram_bank_flags = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_ram_bank_flags = qat_comp_get_ram_bank_flags_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_set_slice_cfg_word = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_set_slice_cfg_word = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_set_slice_cfg_word = qat_comp_set_slice_cfg_word_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_feature_flags = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_feature_flags = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_feature_flags = qat_comp_get_features_gen1; } diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c index 6fb8cf69be..815276fc9e 100644 --- a/drivers/compress/qat/qat_comp_pmd.c +++ b/drivers/compress/qat/qat_comp_pmd.c @@ -682,11 +682,18 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev, const struct qat_comp_gen_dev_ops *qat_comp_gen_ops = &qat_comp_gen_dev_ops[qat_pci_dev->qat_dev_gen]; uint64_t capa_size; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s", qat_pci_dev->name, "comp"); QAT_LOG(DEBUG, "Creating QAT COMP device %s", name); + if (qat_pci_dev->qat_dev_gen == QAT_VQAT && + sub_id != ADF_VQAT_DC_PCI_SUBSYSTEM_ID) { + QAT_LOG(ERR, "Device (vqat instance) %s does not support compression", + name); + return -EFAULT; + } if (qat_comp_gen_ops->compressdev_ops == NULL) { QAT_LOG(DEBUG, "Device %s does not support compression", name); return -ENOTSUP; diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c index de72383d4b..d399073f5e 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c @@ -406,14 +406,18 @@ qat_sym_configure_raw_dp_ctx_gen4(void *_raw_dp_ctx, void *_ctx) RTE_INIT(qat_sym_crypto_gen4_init) { - qat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1; - qat_sym_gen_dev_ops[QAT_GEN4].get_capabilities = + qat_sym_gen_dev_ops[QAT_VQAT].cryptodev_ops = + qat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1; + qat_sym_gen_dev_ops[QAT_VQAT].get_capabilities = + qat_sym_gen_dev_ops[QAT_GEN4].get_capabilities = qat_sym_crypto_cap_get_gen4; - qat_sym_gen_dev_ops[QAT_GEN4].set_session = + qat_sym_gen_dev_ops[QAT_VQAT].set_session = + qat_sym_gen_dev_ops[QAT_GEN4].set_session = qat_sym_crypto_set_session_gen4; qat_sym_gen_dev_ops[QAT_GEN4].set_raw_dp_ctx = qat_sym_configure_raw_dp_ctx_gen4; - qat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags = + qat_sym_gen_dev_ops[QAT_VQAT].get_feature_flags = + qat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags = qat_sym_crypto_feature_flags_get_gen1; qat_sym_gen_dev_ops[QAT_GEN4].create_security_ctx = qat_sym_create_security_gen1; @@ -421,12 +425,16 @@ RTE_INIT(qat_sym_crypto_gen4_init) RTE_INIT(qat_asym_crypto_gen4_init) { - qat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops = + qat_asym_gen_dev_ops[QAT_VQAT].cryptodev_ops = + qat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_asym_crypto_ops_gen1; - qat_asym_gen_dev_ops[QAT_GEN4].get_capabilities = + qat_asym_gen_dev_ops[QAT_VQAT].get_capabilities = + qat_asym_gen_dev_ops[QAT_GEN4].get_capabilities = qat_asym_crypto_cap_get_gen1; - qat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags = + qat_asym_gen_dev_ops[QAT_VQAT].get_feature_flags = + qat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags = qat_asym_crypto_feature_flags_get_gen1; - qat_asym_gen_dev_ops[QAT_GEN4].set_session = + qat_asym_gen_dev_ops[QAT_VQAT].set_session = + qat_asym_gen_dev_ops[QAT_GEN4].set_session = qat_asym_crypto_set_session_gen1; } diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c index 2bf3060278..d96eb7ec6d 100644 --- a/drivers/crypto/qat/qat_asym.c +++ b/drivers/crypto/qat/qat_asym.c @@ -1517,11 +1517,18 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev, char capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN]; int i = 0; uint16_t slice_map = 0; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s", qat_pci_dev->name, "asym"); QAT_LOG(DEBUG, "Creating QAT ASYM device %s\n", name); + if (qat_pci_dev->qat_dev_gen == QAT_VQAT && + sub_id != ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID) { + QAT_LOG(ERR, "Device (vqat instance) %s does not support asymmetric crypto", + name); + return -EFAULT; + } if (gen_dev_ops->cryptodev_ops == NULL) { QAT_LOG(ERR, "Device %s does not support asymmetric crypto", name); diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c index 6e03bde841..6301fdec0e 100644 --- a/drivers/crypto/qat/qat_sym.c +++ b/drivers/crypto/qat/qat_sym.c @@ -202,11 +202,18 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev, struct qat_cryptodev_private *internals; const struct qat_crypto_gen_dev_ops *gen_dev_ops = &qat_sym_gen_dev_ops[qat_pci_dev->qat_dev_gen]; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s", qat_pci_dev->name, "sym"); QAT_LOG(DEBUG, "Creating QAT SYM device %s", name); + if (qat_pci_dev->qat_dev_gen == QAT_VQAT && + sub_id != ADF_VQAT_SYM_PCI_SUBSYSTEM_ID) { + QAT_LOG(ERR, "Device (vqat instance) %s does not support symmetric crypto", + name); + return -EFAULT; + } if (gen_dev_ops->cryptodev_ops == NULL) { QAT_LOG(ERR, "Device %s does not support symmetric crypto", name); diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index 9f4f6c3d93..1df990b596 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -405,7 +405,7 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev, goto error_out; } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; break; case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: @@ -911,7 +911,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, session->auth_iv.length = AES_GCM_J0_LEN; else session->is_iv12B = 1; - if (qat_dev_gen == QAT_GEN4) { + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) { session->is_cnt_zero = 1; session->is_ucs = 1; } @@ -1039,7 +1039,7 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev, session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; if (session->cipher_iv.length == 0) { session->cipher_iv.length = AES_GCM_J0_LEN; @@ -1059,13 +1059,13 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev, } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; break; case RTE_CRYPTO_AEAD_CHACHA20_POLY1305: if (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ) return -EINVAL; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305; @@ -2298,7 +2298,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc, auth_param->u2.inner_prefix_sz = qat_hash_get_block_size(cdesc->qat_hash_alg); auth_param->hash_state_sz = digestsize; - if (qat_dev_gen == QAT_GEN4) { + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) { ICP_QAT_FW_HASH_FLAG_MODE2_SET( hash_cd_ctrl->hash_flags, QAT_FW_LA_MODE2); @@ -2840,6 +2840,7 @@ qat_sym_cd_crc_set(struct qat_sym_session *cdesc, cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_gen3_crc_cd); break; case QAT_GEN4: + case QAT_VQAT: crc_cfg.mode = ICP_QAT_HW_CIPHER_ECB_MODE; crc_cfg.algo = ICP_QAT_HW_CIPHER_ALGO_NULL; crc_cfg.hash_cmp_val = 0; -- 2.34.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v3] common/qat: add virtual qat device (vQAT) 2024-02-21 7:50 ` [PATCH v3] common/qat: add " Arkadiusz Kusztal @ 2024-02-22 12:20 ` Power, Ciara 2024-02-29 10:21 ` [PATCH v4] " Arkadiusz Kusztal 1 sibling, 0 replies; 12+ messages in thread From: Power, Ciara @ 2024-02-22 12:20 UTC (permalink / raw) To: Kusztal, ArkadiuszX, dev; +Cc: gakhil Hi Arek, > -----Original Message----- > From: Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com> > Sent: Wednesday, February 21, 2024 7:50 AM > To: dev@dpdk.org > Cc: gakhil@marvell.com; Power, Ciara <ciara.power@intel.com>; Kusztal, > ArkadiuszX <arkadiuszx.kusztal@intel.com> > Subject: [PATCH v3] common/qat: add virtual qat device (vQAT) > > This commit adds virtual QAT device to the Intel QuickAssist Technology PMD. > There are three kinds of virtual QAT device defined which offer different QAT > service to the customers: symmetric crypto, asymmetric crypto and > compression. > > Signed-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com> > --- > v2: > - added symmetric crypto qp config > v3: > - added compression > - added asymmetric crypto <snip> Acked-by: Ciara Power <ciara.power@intel.com> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4] common/qat: add virtual qat device (vQAT) 2024-02-21 7:50 ` [PATCH v3] common/qat: add " Arkadiusz Kusztal 2024-02-22 12:20 ` Power, Ciara @ 2024-02-29 10:21 ` Arkadiusz Kusztal 2024-02-29 10:27 ` Power, Ciara ` (2 more replies) 1 sibling, 3 replies; 12+ messages in thread From: Arkadiusz Kusztal @ 2024-02-29 10:21 UTC (permalink / raw) To: dev; +Cc: gakhil, ciara.power, Arkadiusz Kusztal This commit adds virtual QAT device to the Intel QuickAssist Technology PMD. There are three kinds of virtual QAT device defined which offer different QAT service to the customers: symmetric crypto, asymmetric crypto and compression. Signed-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com> --- v2: - added symmetric crypto qp config v3: - added compression - added asymmetric crypto v4: - rebased to fix a release notes issue doc/guides/rel_notes/release_24_03.rst | 4 ++ drivers/common/qat/dev/qat_dev_gen4.c | 55 +++++++++++++++++++++++++++- drivers/common/qat/qat_adf/icp_qat_hw.h | 5 +++ drivers/common/qat/qat_common.h | 1 + drivers/common/qat/qat_device.c | 7 +++- drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 18 ++++++--- drivers/compress/qat/qat_comp_pmd.c | 7 ++++ drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 24 ++++++++---- drivers/crypto/qat/qat_asym.c | 7 ++++ drivers/crypto/qat/qat_sym.c | 7 ++++ drivers/crypto/qat/qat_sym_session.c | 13 ++++--- 11 files changed, 126 insertions(+), 22 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 879bb4944c..76a9e7230a 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -138,6 +138,10 @@ New Features to support TLS v1.2, TLS v1.3 and DTLS v1.2. * Added PMD API to allow raw submission of instructions to CPT. +* **Updated Intel QuickAssist Technology driver.** + + * Enabled support for virtual QAT - vQAT (0da5) devices in QAT PMD. + Removed Items ------------- diff --git a/drivers/common/qat/dev/qat_dev_gen4.c b/drivers/common/qat/dev/qat_dev_gen4.c index 1ce262f715..1c5a2f2b6f 100644 --- a/drivers/common/qat/dev/qat_dev_gen4.c +++ b/drivers/common/qat/dev/qat_dev_gen4.c @@ -143,6 +143,42 @@ qat_dev_read_config_gen4(struct qat_pci_device *qat_dev) return 0; } +static int +qat_dev_read_config_vqat(struct qat_pci_device *qat_dev) +{ + int i = 0; + struct qat_dev_gen4_extra *dev_extra = qat_dev->dev_private; + struct qat_qp_hw_data *hw_data; + struct qat_device_info *qat_dev_instance = + &qat_pci_devs[qat_dev->qat_dev_id]; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; + + for (; i < QAT_GEN4_BUNDLE_NUM; i++) { + hw_data = &dev_extra->qp_gen4_data[i][0]; + memset(hw_data, 0, sizeof(*hw_data)); + if (sub_id == ADF_VQAT_SYM_PCI_SUBSYSTEM_ID) { + hw_data->service_type = QAT_SERVICE_SYMMETRIC; + hw_data->tx_msg_size = 128; + hw_data->rx_msg_size = 32; + } else if (sub_id == ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID) { + hw_data->service_type = QAT_SERVICE_ASYMMETRIC; + hw_data->tx_msg_size = 64; + hw_data->rx_msg_size = 32; + } else if (sub_id == ADF_VQAT_DC_PCI_SUBSYSTEM_ID) { + hw_data->service_type = QAT_SERVICE_COMPRESSION; + hw_data->tx_msg_size = 128; + hw_data->rx_msg_size = 32; + } else { + QAT_LOG(ERR, "Unrecognized subsystem id %hu", sub_id); + return -EINVAL; + } + hw_data->tx_ring_num = 0; + hw_data->rx_ring_num = 1; + hw_data->hw_bundle_num = i; + } + return 0; +} + static void qat_qp_build_ring_base_gen4(void *io_addr, struct qat_queue *queue) @@ -268,6 +304,12 @@ qat_reset_ring_pairs_gen4(struct qat_pci_device *qat_pci_dev) return 0; } +static int +qat_reset_ring_pairs_vqat(struct qat_pci_device *qat_pci_dev __rte_unused) +{ + return 0; +} + static const struct rte_mem_resource * qat_dev_get_transport_bar_gen4(struct rte_pci_device *pci_dev) { @@ -304,10 +346,21 @@ static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen4 = { .qat_dev_get_slice_map = qat_dev_get_slice_map_gen4, }; +static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_vqat = { + .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_vqat, + .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen4, + .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen4, + .qat_dev_read_config = qat_dev_read_config_vqat, + .qat_dev_get_extra_size = qat_dev_get_extra_size_gen4, + .qat_dev_get_slice_map = qat_dev_get_slice_map_gen4, +}; + RTE_INIT(qat_dev_gen_4_init) { - qat_qp_hw_spec[QAT_GEN4] = &qat_qp_hw_spec_gen4; + qat_qp_hw_spec[QAT_VQAT] = qat_qp_hw_spec[QAT_GEN4] = &qat_qp_hw_spec_gen4; qat_dev_hw_spec[QAT_GEN4] = &qat_dev_hw_spec_gen4; + qat_dev_hw_spec[QAT_VQAT] = &qat_dev_hw_spec_vqat; qat_gen_config[QAT_GEN4].dev_gen = QAT_GEN4; + qat_gen_config[QAT_VQAT].dev_gen = QAT_VQAT; qat_gen_config[QAT_GEN4].pf2vf_dev = &qat_pf2vf_gen4; } diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h index 33756d512d..fc047bc2a6 100644 --- a/drivers/common/qat/qat_adf/icp_qat_hw.h +++ b/drivers/common/qat/qat_adf/icp_qat_hw.h @@ -9,6 +9,11 @@ #define ADF_C4XXXIOV_VFLEGFUSES_OFFSET 0x4C #define ADF1_C4XXXIOV_VFLEGFUSES_LEN 4 +/* Definition of virtual QAT subsystem ID*/ +#define ADF_VQAT_SYM_PCI_SUBSYSTEM_ID 0x00 +#define ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID 0x01 +#define ADF_VQAT_DC_PCI_SUBSYSTEM_ID 0x02 + enum icp_qat_slice_mask { ICP_ACCEL_MASK_CIPHER_SLICE = 0x01, ICP_ACCEL_MASK_AUTH_SLICE = 0x02, diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h index 9411a79301..53799ce174 100644 --- a/drivers/common/qat/qat_common.h +++ b/drivers/common/qat/qat_common.h @@ -21,6 +21,7 @@ enum qat_device_gen { QAT_GEN2, QAT_GEN3, QAT_GEN4, + QAT_VQAT, QAT_N_GENS }; diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c index f55dc3c6f0..a9ea4af5df 100644 --- a/drivers/common/qat/qat_device.c +++ b/drivers/common/qat/qat_device.c @@ -62,6 +62,9 @@ static const struct rte_pci_id pci_id_qat_map[] = { { RTE_PCI_DEVICE(0x8086, 0x4945), }, + { + RTE_PCI_DEVICE(0x8086, 0x0da5), + }, {.device_id = 0}, }; @@ -199,6 +202,8 @@ pick_gen(const struct rte_pci_device *pci_dev) case 0x4943: case 0x4945: return QAT_GEN4; + case 0x0da5: + return QAT_VQAT; default: QAT_LOG(ERR, "Invalid dev_id, can't determine generation"); return QAT_N_GENS; @@ -281,6 +286,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev, strlcpy(qat_dev->name, name, QAT_DEV_NAME_MAX_LEN); qat_dev->qat_dev_id = qat_dev_id; qat_dev->qat_dev_gen = qat_dev_gen; + qat_pci_devs[qat_dev_id].pci_dev = pci_dev; ops_hw = qat_dev_hw_spec[qat_dev->qat_dev_gen]; NOT_NULL(ops_hw->qat_dev_get_misc_bar, goto error, @@ -326,7 +332,6 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev, * qat_dev to list of devices */ qat_pci_devs[qat_dev_id].mz = qat_dev_mz; - qat_pci_devs[qat_dev_id].pci_dev = pci_dev; qat_nb_pci_devices++; QAT_LOG(DEBUG, "QAT device %d found, name %s, total QATs %d", diff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c index 05906f13e0..d3de73a02f 100644 --- a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c +++ b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c @@ -198,16 +198,22 @@ qat_comp_get_num_im_bufs_required_gen4(void) RTE_INIT(qat_comp_pmd_gen4_init) { - qat_comp_gen_dev_ops[QAT_GEN4].compressdev_ops = + qat_comp_gen_dev_ops[QAT_VQAT].compressdev_ops = + qat_comp_gen_dev_ops[QAT_GEN4].compressdev_ops = &qat_comp_ops_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_capabilities = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_capabilities = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_capabilities = qat_comp_cap_get_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_num_im_bufs_required = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_num_im_bufs_required = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_num_im_bufs_required = qat_comp_get_num_im_bufs_required_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_ram_bank_flags = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_ram_bank_flags = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_ram_bank_flags = qat_comp_get_ram_bank_flags_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_set_slice_cfg_word = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_set_slice_cfg_word = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_set_slice_cfg_word = qat_comp_set_slice_cfg_word_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_feature_flags = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_feature_flags = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_feature_flags = qat_comp_get_features_gen1; } diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c index 6fb8cf69be..815276fc9e 100644 --- a/drivers/compress/qat/qat_comp_pmd.c +++ b/drivers/compress/qat/qat_comp_pmd.c @@ -682,11 +682,18 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev, const struct qat_comp_gen_dev_ops *qat_comp_gen_ops = &qat_comp_gen_dev_ops[qat_pci_dev->qat_dev_gen]; uint64_t capa_size; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s", qat_pci_dev->name, "comp"); QAT_LOG(DEBUG, "Creating QAT COMP device %s", name); + if (qat_pci_dev->qat_dev_gen == QAT_VQAT && + sub_id != ADF_VQAT_DC_PCI_SUBSYSTEM_ID) { + QAT_LOG(ERR, "Device (vqat instance) %s does not support compression", + name); + return -EFAULT; + } if (qat_comp_gen_ops->compressdev_ops == NULL) { QAT_LOG(DEBUG, "Device %s does not support compression", name); return -ENOTSUP; diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c index de72383d4b..d399073f5e 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c @@ -406,14 +406,18 @@ qat_sym_configure_raw_dp_ctx_gen4(void *_raw_dp_ctx, void *_ctx) RTE_INIT(qat_sym_crypto_gen4_init) { - qat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1; - qat_sym_gen_dev_ops[QAT_GEN4].get_capabilities = + qat_sym_gen_dev_ops[QAT_VQAT].cryptodev_ops = + qat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1; + qat_sym_gen_dev_ops[QAT_VQAT].get_capabilities = + qat_sym_gen_dev_ops[QAT_GEN4].get_capabilities = qat_sym_crypto_cap_get_gen4; - qat_sym_gen_dev_ops[QAT_GEN4].set_session = + qat_sym_gen_dev_ops[QAT_VQAT].set_session = + qat_sym_gen_dev_ops[QAT_GEN4].set_session = qat_sym_crypto_set_session_gen4; qat_sym_gen_dev_ops[QAT_GEN4].set_raw_dp_ctx = qat_sym_configure_raw_dp_ctx_gen4; - qat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags = + qat_sym_gen_dev_ops[QAT_VQAT].get_feature_flags = + qat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags = qat_sym_crypto_feature_flags_get_gen1; qat_sym_gen_dev_ops[QAT_GEN4].create_security_ctx = qat_sym_create_security_gen1; @@ -421,12 +425,16 @@ RTE_INIT(qat_sym_crypto_gen4_init) RTE_INIT(qat_asym_crypto_gen4_init) { - qat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops = + qat_asym_gen_dev_ops[QAT_VQAT].cryptodev_ops = + qat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_asym_crypto_ops_gen1; - qat_asym_gen_dev_ops[QAT_GEN4].get_capabilities = + qat_asym_gen_dev_ops[QAT_VQAT].get_capabilities = + qat_asym_gen_dev_ops[QAT_GEN4].get_capabilities = qat_asym_crypto_cap_get_gen1; - qat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags = + qat_asym_gen_dev_ops[QAT_VQAT].get_feature_flags = + qat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags = qat_asym_crypto_feature_flags_get_gen1; - qat_asym_gen_dev_ops[QAT_GEN4].set_session = + qat_asym_gen_dev_ops[QAT_VQAT].set_session = + qat_asym_gen_dev_ops[QAT_GEN4].set_session = qat_asym_crypto_set_session_gen1; } diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c index 2bf3060278..d96eb7ec6d 100644 --- a/drivers/crypto/qat/qat_asym.c +++ b/drivers/crypto/qat/qat_asym.c @@ -1517,11 +1517,18 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev, char capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN]; int i = 0; uint16_t slice_map = 0; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s", qat_pci_dev->name, "asym"); QAT_LOG(DEBUG, "Creating QAT ASYM device %s\n", name); + if (qat_pci_dev->qat_dev_gen == QAT_VQAT && + sub_id != ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID) { + QAT_LOG(ERR, "Device (vqat instance) %s does not support asymmetric crypto", + name); + return -EFAULT; + } if (gen_dev_ops->cryptodev_ops == NULL) { QAT_LOG(ERR, "Device %s does not support asymmetric crypto", name); diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c index 6e03bde841..6301fdec0e 100644 --- a/drivers/crypto/qat/qat_sym.c +++ b/drivers/crypto/qat/qat_sym.c @@ -202,11 +202,18 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev, struct qat_cryptodev_private *internals; const struct qat_crypto_gen_dev_ops *gen_dev_ops = &qat_sym_gen_dev_ops[qat_pci_dev->qat_dev_gen]; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s", qat_pci_dev->name, "sym"); QAT_LOG(DEBUG, "Creating QAT SYM device %s", name); + if (qat_pci_dev->qat_dev_gen == QAT_VQAT && + sub_id != ADF_VQAT_SYM_PCI_SUBSYSTEM_ID) { + QAT_LOG(ERR, "Device (vqat instance) %s does not support symmetric crypto", + name); + return -EFAULT; + } if (gen_dev_ops->cryptodev_ops == NULL) { QAT_LOG(ERR, "Device %s does not support symmetric crypto", name); diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index 9f4f6c3d93..1df990b596 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -405,7 +405,7 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev, goto error_out; } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; break; case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: @@ -911,7 +911,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, session->auth_iv.length = AES_GCM_J0_LEN; else session->is_iv12B = 1; - if (qat_dev_gen == QAT_GEN4) { + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) { session->is_cnt_zero = 1; session->is_ucs = 1; } @@ -1039,7 +1039,7 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev, session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; if (session->cipher_iv.length == 0) { session->cipher_iv.length = AES_GCM_J0_LEN; @@ -1059,13 +1059,13 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev, } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; break; case RTE_CRYPTO_AEAD_CHACHA20_POLY1305: if (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ) return -EINVAL; - if (qat_dev_gen == QAT_GEN4) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) session->is_ucs = 1; session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305; @@ -2298,7 +2298,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc, auth_param->u2.inner_prefix_sz = qat_hash_get_block_size(cdesc->qat_hash_alg); auth_param->hash_state_sz = digestsize; - if (qat_dev_gen == QAT_GEN4) { + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_VQAT) { ICP_QAT_FW_HASH_FLAG_MODE2_SET( hash_cd_ctrl->hash_flags, QAT_FW_LA_MODE2); @@ -2840,6 +2840,7 @@ qat_sym_cd_crc_set(struct qat_sym_session *cdesc, cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_gen3_crc_cd); break; case QAT_GEN4: + case QAT_VQAT: crc_cfg.mode = ICP_QAT_HW_CIPHER_ECB_MODE; crc_cfg.algo = ICP_QAT_HW_CIPHER_ALGO_NULL; crc_cfg.hash_cmp_val = 0; -- 2.13.6 ^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v4] common/qat: add virtual qat device (vQAT) 2024-02-29 10:21 ` [PATCH v4] " Arkadiusz Kusztal @ 2024-02-29 10:27 ` Power, Ciara 2024-03-01 6:15 ` [EXTERNAL] " Akhil Goyal 2024-03-01 15:19 ` [PATCH v5] " Arkadiusz Kusztal 2 siblings, 0 replies; 12+ messages in thread From: Power, Ciara @ 2024-02-29 10:27 UTC (permalink / raw) To: Kusztal, ArkadiuszX, dev; +Cc: gakhil > -----Original Message----- > From: Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com> > Sent: Thursday, February 29, 2024 10:22 AM > To: dev@dpdk.org > Cc: gakhil@marvell.com; Power, Ciara <ciara.power@intel.com>; Kusztal, > ArkadiuszX <arkadiuszx.kusztal@intel.com> > Subject: [PATCH v4] common/qat: add virtual qat device (vQAT) > > This commit adds virtual QAT device to the Intel QuickAssist Technology PMD. > There are three kinds of virtual QAT device defined which offer different QAT > service to the customers: symmetric crypto, asymmetric crypto and > compression. > > Signed-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com> > --- > v2: > - added symmetric crypto qp config > v3: > - added compression > - added asymmetric crypto > v4: > - rebased to fix a release notes issue > > doc/guides/rel_notes/release_24_03.rst | 4 ++ > drivers/common/qat/dev/qat_dev_gen4.c | 55 > +++++++++++++++++++++++++++- > drivers/common/qat/qat_adf/icp_qat_hw.h | 5 +++ > drivers/common/qat/qat_common.h | 1 + > drivers/common/qat/qat_device.c | 7 +++- > drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 18 ++++++--- > drivers/compress/qat/qat_comp_pmd.c | 7 ++++ > drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 24 ++++++++---- > drivers/crypto/qat/qat_asym.c | 7 ++++ > drivers/crypto/qat/qat_sym.c | 7 ++++ > drivers/crypto/qat/qat_sym_session.c | 13 ++++--- > 11 files changed, 126 insertions(+), 22 deletions(-) Acked-by: Ciara Power <ciara.power@intel.com> ^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [EXTERNAL] [PATCH v4] common/qat: add virtual qat device (vQAT) 2024-02-29 10:21 ` [PATCH v4] " Arkadiusz Kusztal 2024-02-29 10:27 ` Power, Ciara @ 2024-03-01 6:15 ` Akhil Goyal 2024-03-01 15:19 ` [PATCH v5] " Arkadiusz Kusztal 2 siblings, 0 replies; 12+ messages in thread From: Akhil Goyal @ 2024-03-01 6:15 UTC (permalink / raw) To: Arkadiusz Kusztal, dev; +Cc: ciara.power > This commit adds virtual QAT device to the Intel > QuickAssist Technology PMD. There are three kinds of > virtual QAT device defined which offer different QAT > service to the customers: symmetric crypto, asymmetric > crypto and compression. > > Signed-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com> > --- Please rebase. ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5] common/qat: add virtual qat device (vQAT) 2024-02-29 10:21 ` [PATCH v4] " Arkadiusz Kusztal 2024-02-29 10:27 ` Power, Ciara 2024-03-01 6:15 ` [EXTERNAL] " Akhil Goyal @ 2024-03-01 15:19 ` Arkadiusz Kusztal 2024-03-01 15:24 ` [EXTERNAL] " Akhil Goyal 2024-03-01 15:48 ` Ji, Kai 2 siblings, 2 replies; 12+ messages in thread From: Arkadiusz Kusztal @ 2024-03-01 15:19 UTC (permalink / raw) To: dev; +Cc: gakhil, ciara.power, Arkadiusz Kusztal This commit adds virtual QAT device to the Intel QuickAssist Technology PMD. There are three kinds of virtual QAT device defined which offer different QAT service to the customers: symmetric crypto, asymmetric crypto and compression. Signed-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com> --- v2: - added symmetric crypto qp config v3: - added compression - added asymmetric crypto v4: - rebased to fix a release notes issue v5: - rebased against newest changes to the pmd doc/guides/rel_notes/release_24_03.rst | 4 ++ drivers/common/qat/dev/qat_dev_gen4.c | 55 +++++++++++++++++++++++++++- drivers/common/qat/qat_adf/icp_qat_hw.h | 5 +++ drivers/common/qat/qat_common.h | 1 + drivers/common/qat/qat_device.c | 7 +++- drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 18 ++++++--- drivers/compress/qat/qat_comp_pmd.c | 7 ++++ drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 24 ++++++++---- drivers/crypto/qat/qat_asym.c | 7 ++++ drivers/crypto/qat/qat_sym.c | 7 ++++ drivers/crypto/qat/qat_sym_session.c | 18 ++++++--- 11 files changed, 131 insertions(+), 22 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index dc498a29ce..0ba9b3c569 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -146,6 +146,10 @@ New Features to support TLS v1.2, TLS v1.3 and DTLS v1.2. * Added PMD API to allow raw submission of instructions to CPT. +* **Updated Intel QuickAssist Technology driver.** + + * Enabled support for virtual QAT - vQAT (0da5) devices in QAT PMD. + Removed Items ------------- diff --git a/drivers/common/qat/dev/qat_dev_gen4.c b/drivers/common/qat/dev/qat_dev_gen4.c index 2525e1e695..b7a6321e79 100644 --- a/drivers/common/qat/dev/qat_dev_gen4.c +++ b/drivers/common/qat/dev/qat_dev_gen4.c @@ -144,6 +144,42 @@ qat_dev_read_config_gen4(struct qat_pci_device *qat_dev) return 0; } +static int +qat_dev_read_config_vqat(struct qat_pci_device *qat_dev) +{ + int i = 0; + struct qat_dev_gen4_extra *dev_extra = qat_dev->dev_private; + struct qat_qp_hw_data *hw_data; + struct qat_device_info *qat_dev_instance = + &qat_pci_devs[qat_dev->qat_dev_id]; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; + + for (; i < QAT_GEN4_BUNDLE_NUM; i++) { + hw_data = &dev_extra->qp_gen4_data[i][0]; + memset(hw_data, 0, sizeof(*hw_data)); + if (sub_id == ADF_VQAT_SYM_PCI_SUBSYSTEM_ID) { + hw_data->service_type = QAT_SERVICE_SYMMETRIC; + hw_data->tx_msg_size = 128; + hw_data->rx_msg_size = 32; + } else if (sub_id == ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID) { + hw_data->service_type = QAT_SERVICE_ASYMMETRIC; + hw_data->tx_msg_size = 64; + hw_data->rx_msg_size = 32; + } else if (sub_id == ADF_VQAT_DC_PCI_SUBSYSTEM_ID) { + hw_data->service_type = QAT_SERVICE_COMPRESSION; + hw_data->tx_msg_size = 128; + hw_data->rx_msg_size = 32; + } else { + QAT_LOG(ERR, "Unrecognized subsystem id %hu", sub_id); + return -EINVAL; + } + hw_data->tx_ring_num = 0; + hw_data->rx_ring_num = 1; + hw_data->hw_bundle_num = i; + } + return 0; +} + void qat_qp_build_ring_base_gen4(void *io_addr, struct qat_queue *queue) @@ -269,6 +305,12 @@ qat_reset_ring_pairs_gen4(struct qat_pci_device *qat_pci_dev) return 0; } +static int +qat_reset_ring_pairs_vqat(struct qat_pci_device *qat_pci_dev __rte_unused) +{ + return 0; +} + const struct rte_mem_resource * qat_dev_get_transport_bar_gen4(struct rte_pci_device *pci_dev) { @@ -305,10 +347,21 @@ static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen4 = { .qat_dev_get_slice_map = qat_dev_get_slice_map_gen4, }; +static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_vqat = { + .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_vqat, + .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen4, + .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen4, + .qat_dev_read_config = qat_dev_read_config_vqat, + .qat_dev_get_extra_size = qat_dev_get_extra_size_gen4, + .qat_dev_get_slice_map = qat_dev_get_slice_map_gen4, +}; + RTE_INIT(qat_dev_gen_4_init) { - qat_qp_hw_spec[QAT_GEN4] = &qat_qp_hw_spec_gen4; + qat_qp_hw_spec[QAT_VQAT] = qat_qp_hw_spec[QAT_GEN4] = &qat_qp_hw_spec_gen4; qat_dev_hw_spec[QAT_GEN4] = &qat_dev_hw_spec_gen4; + qat_dev_hw_spec[QAT_VQAT] = &qat_dev_hw_spec_vqat; qat_gen_config[QAT_GEN4].dev_gen = QAT_GEN4; + qat_gen_config[QAT_VQAT].dev_gen = QAT_VQAT; qat_gen_config[QAT_GEN4].pf2vf_dev = &qat_pf2vf_gen4; } diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h index b99dde2176..21ee3cf8fd 100644 --- a/drivers/common/qat/qat_adf/icp_qat_hw.h +++ b/drivers/common/qat/qat_adf/icp_qat_hw.h @@ -9,6 +9,11 @@ #define ADF_C4XXXIOV_VFLEGFUSES_OFFSET 0x4C #define ADF1_C4XXXIOV_VFLEGFUSES_LEN 4 +/* Definition of virtual QAT subsystem ID*/ +#define ADF_VQAT_SYM_PCI_SUBSYSTEM_ID 0x00 +#define ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID 0x01 +#define ADF_VQAT_DC_PCI_SUBSYSTEM_ID 0x02 + enum icp_qat_slice_mask { ICP_ACCEL_MASK_CIPHER_SLICE = 0x01, ICP_ACCEL_MASK_AUTH_SLICE = 0x02, diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h index 44a8dff802..12f281e5b1 100644 --- a/drivers/common/qat/qat_common.h +++ b/drivers/common/qat/qat_common.h @@ -23,6 +23,7 @@ enum qat_device_gen { QAT_GEN4, QAT_GEN5, QAT_GEN_LCE, + QAT_VQAT, QAT_N_GENS }; diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c index a77c628256..09347845e0 100644 --- a/drivers/common/qat/qat_device.c +++ b/drivers/common/qat/qat_device.c @@ -71,6 +71,9 @@ static const struct rte_pci_id pci_id_qat_map[] = { { RTE_PCI_DEVICE(0x8086, 0x1454), }, + { + RTE_PCI_DEVICE(0x8086, 0x0da5), + }, {.device_id = 0}, }; @@ -213,6 +216,8 @@ pick_gen(const struct rte_pci_device *pci_dev) return QAT_GEN5; case 0x1454: return QAT_GEN_LCE; + case 0x0da5: + return QAT_VQAT; default: QAT_LOG(ERR, "Invalid dev_id, can't determine generation"); return QAT_N_GENS; @@ -302,6 +307,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev, strlcpy(qat_dev->name, name, QAT_DEV_NAME_MAX_LEN); qat_dev->qat_dev_id = qat_dev_id; qat_dev->qat_dev_gen = qat_dev_gen; + qat_pci_devs[qat_dev_id].pci_dev = pci_dev; if (wireless_slice_support(pci_dev->id.device_id)) qat_dev->has_wireless_slice = 1; @@ -350,7 +356,6 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev, * qat_dev to list of devices */ qat_pci_devs[qat_dev_id].mz = qat_dev_mz; - qat_pci_devs[qat_dev_id].pci_dev = pci_dev; qat_nb_pci_devices++; QAT_LOG(DEBUG, "QAT device %d found, name %s, total QATs %d", diff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c index 68d111e07c..f177ba2309 100644 --- a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c +++ b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c @@ -198,16 +198,22 @@ qat_comp_get_num_im_bufs_required_gen4(void) RTE_INIT(qat_comp_pmd_gen4_init) { - qat_comp_gen_dev_ops[QAT_GEN4].compressdev_ops = + qat_comp_gen_dev_ops[QAT_VQAT].compressdev_ops = + qat_comp_gen_dev_ops[QAT_GEN4].compressdev_ops = &qat_comp_ops_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_capabilities = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_capabilities = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_capabilities = qat_comp_cap_get_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_num_im_bufs_required = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_num_im_bufs_required = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_num_im_bufs_required = qat_comp_get_num_im_bufs_required_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_ram_bank_flags = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_ram_bank_flags = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_ram_bank_flags = qat_comp_get_ram_bank_flags_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_set_slice_cfg_word = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_set_slice_cfg_word = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_set_slice_cfg_word = qat_comp_set_slice_cfg_word_gen4; - qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_feature_flags = + qat_comp_gen_dev_ops[QAT_VQAT].qat_comp_get_feature_flags = + qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_feature_flags = qat_comp_get_features_gen1; } diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c index 6fb8cf69be..815276fc9e 100644 --- a/drivers/compress/qat/qat_comp_pmd.c +++ b/drivers/compress/qat/qat_comp_pmd.c @@ -682,11 +682,18 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev, const struct qat_comp_gen_dev_ops *qat_comp_gen_ops = &qat_comp_gen_dev_ops[qat_pci_dev->qat_dev_gen]; uint64_t capa_size; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; snprintf(name, RTE_COMPRESSDEV_NAME_MAX_LEN, "%s_%s", qat_pci_dev->name, "comp"); QAT_LOG(DEBUG, "Creating QAT COMP device %s", name); + if (qat_pci_dev->qat_dev_gen == QAT_VQAT && + sub_id != ADF_VQAT_DC_PCI_SUBSYSTEM_ID) { + QAT_LOG(ERR, "Device (vqat instance) %s does not support compression", + name); + return -EFAULT; + } if (qat_comp_gen_ops->compressdev_ops == NULL) { QAT_LOG(DEBUG, "Device %s does not support compression", name); return -ENOTSUP; diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c index 9c7f7d98c8..11f6078759 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c @@ -406,14 +406,18 @@ qat_sym_configure_raw_dp_ctx_gen4(void *_raw_dp_ctx, void *_ctx) RTE_INIT(qat_sym_crypto_gen4_init) { - qat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1; - qat_sym_gen_dev_ops[QAT_GEN4].get_capabilities = + qat_sym_gen_dev_ops[QAT_VQAT].cryptodev_ops = + qat_sym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_sym_crypto_ops_gen1; + qat_sym_gen_dev_ops[QAT_VQAT].get_capabilities = + qat_sym_gen_dev_ops[QAT_GEN4].get_capabilities = qat_sym_crypto_cap_get_gen4; - qat_sym_gen_dev_ops[QAT_GEN4].set_session = + qat_sym_gen_dev_ops[QAT_VQAT].set_session = + qat_sym_gen_dev_ops[QAT_GEN4].set_session = qat_sym_crypto_set_session_gen4; qat_sym_gen_dev_ops[QAT_GEN4].set_raw_dp_ctx = qat_sym_configure_raw_dp_ctx_gen4; - qat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags = + qat_sym_gen_dev_ops[QAT_VQAT].get_feature_flags = + qat_sym_gen_dev_ops[QAT_GEN4].get_feature_flags = qat_sym_crypto_feature_flags_get_gen1; qat_sym_gen_dev_ops[QAT_GEN4].create_security_ctx = qat_sym_create_security_gen1; @@ -421,12 +425,16 @@ RTE_INIT(qat_sym_crypto_gen4_init) RTE_INIT(qat_asym_crypto_gen4_init) { - qat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops = + qat_asym_gen_dev_ops[QAT_VQAT].cryptodev_ops = + qat_asym_gen_dev_ops[QAT_GEN4].cryptodev_ops = &qat_asym_crypto_ops_gen1; - qat_asym_gen_dev_ops[QAT_GEN4].get_capabilities = + qat_asym_gen_dev_ops[QAT_VQAT].get_capabilities = + qat_asym_gen_dev_ops[QAT_GEN4].get_capabilities = qat_asym_crypto_cap_get_gen1; - qat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags = + qat_asym_gen_dev_ops[QAT_VQAT].get_feature_flags = + qat_asym_gen_dev_ops[QAT_GEN4].get_feature_flags = qat_asym_crypto_feature_flags_get_gen1; - qat_asym_gen_dev_ops[QAT_GEN4].set_session = + qat_asym_gen_dev_ops[QAT_VQAT].set_session = + qat_asym_gen_dev_ops[QAT_GEN4].set_session = qat_asym_crypto_set_session_gen1; } diff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c index 2bf3060278..d96eb7ec6d 100644 --- a/drivers/crypto/qat/qat_asym.c +++ b/drivers/crypto/qat/qat_asym.c @@ -1517,11 +1517,18 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev, char capa_memz_name[RTE_CRYPTODEV_NAME_MAX_LEN]; int i = 0; uint16_t slice_map = 0; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s", qat_pci_dev->name, "asym"); QAT_LOG(DEBUG, "Creating QAT ASYM device %s\n", name); + if (qat_pci_dev->qat_dev_gen == QAT_VQAT && + sub_id != ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID) { + QAT_LOG(ERR, "Device (vqat instance) %s does not support asymmetric crypto", + name); + return -EFAULT; + } if (gen_dev_ops->cryptodev_ops == NULL) { QAT_LOG(ERR, "Device %s does not support asymmetric crypto", name); diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c index 9113dfef56..3bf6ce8a75 100644 --- a/drivers/crypto/qat/qat_sym.c +++ b/drivers/crypto/qat/qat_sym.c @@ -209,11 +209,18 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev, enum qat_device_gen qat_dev_gen = qat_pci_dev->qat_dev_gen; const struct qat_crypto_gen_dev_ops *gen_dev_ops = &qat_sym_gen_dev_ops[qat_pci_dev->qat_dev_gen]; + uint16_t sub_id = qat_dev_instance->pci_dev->id.subsystem_device_id; snprintf(name, RTE_CRYPTODEV_NAME_MAX_LEN, "%s_%s", qat_pci_dev->name, "sym"); QAT_LOG(DEBUG, "Creating QAT SYM device %s", name); + if (qat_pci_dev->qat_dev_gen == QAT_VQAT && + sub_id != ADF_VQAT_SYM_PCI_SUBSYSTEM_ID) { + QAT_LOG(ERR, "Device (vqat instance) %s does not support symmetric crypto", + name); + return -EFAULT; + } if (gen_dev_ops->cryptodev_ops == NULL) { QAT_LOG(ERR, "Device %s does not support symmetric crypto", name); diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index e763cfcb51..9e2dba5423 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -410,7 +410,8 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev, goto error_out; } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; - if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 || + qat_dev_gen == QAT_VQAT) session->is_ucs = 1; break; case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: @@ -959,7 +960,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, session->auth_iv.length = AES_GCM_J0_LEN; else session->is_iv12B = 1; - if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5) { + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 || + qat_dev_gen == QAT_VQAT) { session->is_cnt_zero = 1; session->is_ucs = 1; } @@ -1141,7 +1143,8 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev, session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128; - if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 || + qat_dev_gen == QAT_VQAT) session->is_ucs = 1; if (session->cipher_iv.length == 0) { session->cipher_iv.length = AES_GCM_J0_LEN; @@ -1161,13 +1164,15 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev, } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC; - if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 || + qat_dev_gen == QAT_VQAT) session->is_ucs = 1; break; case RTE_CRYPTO_AEAD_CHACHA20_POLY1305: if (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ) return -EINVAL; - if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5) + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 || + qat_dev_gen == QAT_VQAT) session->is_ucs = 1; session->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305; @@ -2469,7 +2474,8 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc, auth_param->u2.inner_prefix_sz = qat_hash_get_block_size(cdesc->qat_hash_alg); auth_param->hash_state_sz = digestsize; - if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5) { + if (qat_dev_gen == QAT_GEN4 || qat_dev_gen == QAT_GEN5 || + qat_dev_gen == QAT_VQAT) { ICP_QAT_FW_HASH_FLAG_MODE2_SET( hash_cd_ctrl->hash_flags, QAT_FW_LA_MODE2); -- 2.13.6 ^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [EXTERNAL] [PATCH v5] common/qat: add virtual qat device (vQAT) 2024-03-01 15:19 ` [PATCH v5] " Arkadiusz Kusztal @ 2024-03-01 15:24 ` Akhil Goyal 2024-03-04 7:07 ` Akhil Goyal 2024-03-01 15:48 ` Ji, Kai 1 sibling, 1 reply; 12+ messages in thread From: Akhil Goyal @ 2024-03-01 15:24 UTC (permalink / raw) To: Arkadiusz Kusztal, dev; +Cc: ciara.power > --- a/doc/guides/rel_notes/release_24_03.rst > +++ b/doc/guides/rel_notes/release_24_03.rst > @@ -146,6 +146,10 @@ New Features > to support TLS v1.2, TLS v1.3 and DTLS v1.2. > * Added PMD API to allow raw submission of instructions to CPT. > > +* **Updated Intel QuickAssist Technology driver.** > + > + * Enabled support for virtual QAT - vQAT (0da5) devices in QAT PMD. > + > You should add QAT updates under the same bullet which is already there for previous updates. I will fix it up while applying but you should take care in future. ^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [EXTERNAL] [PATCH v5] common/qat: add virtual qat device (vQAT) 2024-03-01 15:24 ` [EXTERNAL] " Akhil Goyal @ 2024-03-04 7:07 ` Akhil Goyal 0 siblings, 0 replies; 12+ messages in thread From: Akhil Goyal @ 2024-03-04 7:07 UTC (permalink / raw) To: Arkadiusz Kusztal, dev; +Cc: ciara.power > Subject: RE: [EXTERNAL] [PATCH v5] common/qat: add virtual qat device (vQAT) > > > --- a/doc/guides/rel_notes/release_24_03.rst > > +++ b/doc/guides/rel_notes/release_24_03.rst > > @@ -146,6 +146,10 @@ New Features > > to support TLS v1.2, TLS v1.3 and DTLS v1.2. > > * Added PMD API to allow raw submission of instructions to CPT. > > > > +* **Updated Intel QuickAssist Technology driver.** > > + > > + * Enabled support for virtual QAT - vQAT (0da5) devices in QAT PMD. > > + > > > You should add QAT updates under the same bullet which is already there > for previous updates. > I will fix it up while applying but you should take care in future. Applied to dpdk-next-crypto with above update. Thanks. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5] common/qat: add virtual qat device (vQAT) 2024-03-01 15:19 ` [PATCH v5] " Arkadiusz Kusztal 2024-03-01 15:24 ` [EXTERNAL] " Akhil Goyal @ 2024-03-01 15:48 ` Ji, Kai 1 sibling, 0 replies; 12+ messages in thread From: Ji, Kai @ 2024-03-01 15:48 UTC (permalink / raw) To: Kusztal, ArkadiuszX, dev; +Cc: gakhil, Power, Ciara [-- Attachment #1: Type: text/plain, Size: 1627 bytes --] Acked-by: Kai Ji <kai.ji@intel.com> ________________________________ From: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com> Sent: 01 March 2024 15:19 To: dev@dpdk.org <dev@dpdk.org> Cc: gakhil@marvell.com <gakhil@marvell.com>; Power, Ciara <ciara.power@intel.com>; Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com> Subject: [PATCH v5] common/qat: add virtual qat device (vQAT) This commit adds virtual QAT device to the Intel QuickAssist Technology PMD. There are three kinds of virtual QAT device defined which offer different QAT service to the customers: symmetric crypto, asymmetric crypto and compression. Signed-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com> --- v2: - added symmetric crypto qp config v3: - added compression - added asymmetric crypto v4: - rebased to fix a release notes issue v5: - rebased against newest changes to the pmd doc/guides/rel_notes/release_24_03.rst | 4 ++ drivers/common/qat/dev/qat_dev_gen4.c | 55 +++++++++++++++++++++++++++- drivers/common/qat/qat_adf/icp_qat_hw.h | 5 +++ drivers/common/qat/qat_common.h | 1 + drivers/common/qat/qat_device.c | 7 +++- drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 18 ++++++--- drivers/compress/qat/qat_comp_pmd.c | 7 ++++ drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 24 ++++++++---- drivers/crypto/qat/qat_asym.c | 7 ++++ drivers/crypto/qat/qat_sym.c | 7 ++++ drivers/crypto/qat/qat_sym_session.c | 18 ++++++--- 11 files changed, 131 insertions(+), 22 deletions(-) -- 2.13.6 [-- Attachment #2: Type: text/html, Size: 3242 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2024-03-04 7:07 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-12-18 13:41 [PATCH 1/2] common/qat: add vqat definition to pmd map Arkadiusz Kusztal 2023-12-18 13:41 ` [PATCH 2/2] common/qat: add vqat confiuration macros Arkadiusz Kusztal 2024-02-18 22:25 ` [PATCH v2] common/qat: add symmetric crypto virtual qat device (vQAT) Arkadiusz Kusztal 2024-02-21 7:50 ` [PATCH v3] common/qat: add " Arkadiusz Kusztal 2024-02-22 12:20 ` Power, Ciara 2024-02-29 10:21 ` [PATCH v4] " Arkadiusz Kusztal 2024-02-29 10:27 ` Power, Ciara 2024-03-01 6:15 ` [EXTERNAL] " Akhil Goyal 2024-03-01 15:19 ` [PATCH v5] " Arkadiusz Kusztal 2024-03-01 15:24 ` [EXTERNAL] " Akhil Goyal 2024-03-04 7:07 ` Akhil Goyal 2024-03-01 15:48 ` Ji, Kai
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