From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 870BF437F8; Tue, 2 Jan 2024 05:57:35 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CD9C940E13; Tue, 2 Jan 2024 05:57:07 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 361AE40E68 for ; Tue, 2 Jan 2024 05:57:05 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4020STmC013185 for ; Mon, 1 Jan 2024 20:57:04 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=zrgeQUWtIzFkIWHFi3RZF6VGMwzVE26hoM7FhOC26sk=; b=VRa rdW6NTa8+49NCkTz0253mNCKilRjcYCtXBWbjIER/4zQZ9Juf4UScyhPS2UFQ8DT 3XQAmS2as7TvRus2cZdPNxfAQUQ9erTpVDvtKwnf6Eux7DP0r0Dg7JIl6/7CAHL/ /mkBT3PQ9pWCYXCq2yeAlgraUKkEgOYh47sMhGIi0xJwDxXf+0CbwAmkaBkO8TfI keO9AQI3j4gC+t7ca4nUubYjvMjDz20qrF4rwo4I5Wf4BtoFenYn57+Iw+iTkmjD Nh1gXfSO3X0A4Ce+9EfKQbTkpErWhuIQVFpMqasE5CbetTAkXz2uMsRejPTvClqH zhnUz73mFG9TMs7qCjQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3vb5c346aj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 01 Jan 2024 20:57:04 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 1 Jan 2024 20:57:02 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 1 Jan 2024 20:57:02 -0800 Received: from BG-LT92004.corp.innovium.com (unknown [10.28.163.189]) by maili.marvell.com (Postfix) with ESMTP id 53C493F7081; Mon, 1 Jan 2024 20:56:57 -0800 (PST) From: Anoob Joseph To: Akhil Goyal CC: Tejasree Kondoj , Jerin Jacob , Vidya Sagar Velumuri , Subject: [PATCH v2 24/24] crypto/cnxk: add CPT SG mode debug Date: Tue, 2 Jan 2024 10:24:17 +0530 Message-ID: <20240102045417.115-25-anoobj@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240102045417.115-1-anoobj@marvell.com> References: <20231221123545.510-1-anoobj@marvell.com> <20240102045417.115-1-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: HvkVBa71A1_YN1dqeNu42wdDffyue61o X-Proofpoint-ORIG-GUID: HvkVBa71A1_YN1dqeNu42wdDffyue61o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Tejasree Kondoj Adding CPT SG mode debug dump. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 135 +++++++++++++++++++++- drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 7 ++ 2 files changed, 141 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 9f4be20ff5..8991150c05 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -2,9 +2,10 @@ * Copyright(C) 2021 Marvell. */ -#include #include +#include #include +#include #include #include @@ -103,6 +104,104 @@ cpt_sec_ipsec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, return ret; } +#ifdef CPT_INST_DEBUG_ENABLE +static inline void +cpt_request_data_sgv2_mode_dump(uint8_t *in_buffer, bool glist, uint16_t components) +{ + struct roc_se_buf_ptr list_ptr[ROC_MAX_SG_CNT]; + const char *list = glist ? "glist" : "slist"; + struct roc_sg2list_comp *sg_ptr = NULL; + uint16_t list_cnt = 0; + char suffix[64]; + int i, j; + + sg_ptr = (void *)in_buffer; + for (i = 0; i < components; i++) { + for (j = 0; j < sg_ptr->u.s.valid_segs; j++) { + list_ptr[i * 3 + j].size = sg_ptr->u.s.len[j]; + list_ptr[i * 3 + j].vaddr = (void *)sg_ptr->ptr[j]; + list_ptr[i * 3 + j].vaddr = list_ptr[i * 3 + j].vaddr; + list_cnt++; + } + sg_ptr++; + } + + printf("Current %s: %u\n", list, list_cnt); + + for (i = 0; i < list_cnt; i++) { + snprintf(suffix, sizeof(suffix), "%s[%d]: vaddr 0x%" PRIx64 ", vaddr %p len %u", + list, i, (uint64_t)list_ptr[i].vaddr, list_ptr[i].vaddr, list_ptr[i].size); + rte_hexdump(stdout, suffix, list_ptr[i].vaddr, list_ptr[i].size); + } +} + +static inline void +cpt_request_data_sg_mode_dump(uint8_t *in_buffer, bool glist) +{ + struct roc_se_buf_ptr list_ptr[ROC_MAX_SG_CNT]; + const char *list = glist ? "glist" : "slist"; + struct roc_sglist_comp *sg_ptr = NULL; + uint16_t list_cnt, components; + char suffix[64]; + int i; + + sg_ptr = (void *)(in_buffer + 8); + list_cnt = rte_be_to_cpu_16((((uint16_t *)in_buffer)[2])); + if (!glist) { + components = list_cnt / 4; + if (list_cnt % 4) + components++; + sg_ptr += components; + list_cnt = rte_be_to_cpu_16((((uint16_t *)in_buffer)[3])); + } + + printf("Current %s: %u\n", list, list_cnt); + components = list_cnt / 4; + for (i = 0; i < components; i++) { + list_ptr[i * 4 + 0].size = rte_be_to_cpu_16(sg_ptr->u.s.len[0]); + list_ptr[i * 4 + 1].size = rte_be_to_cpu_16(sg_ptr->u.s.len[1]); + list_ptr[i * 4 + 2].size = rte_be_to_cpu_16(sg_ptr->u.s.len[2]); + list_ptr[i * 4 + 3].size = rte_be_to_cpu_16(sg_ptr->u.s.len[3]); + list_ptr[i * 4 + 0].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[0]); + list_ptr[i * 4 + 1].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[1]); + list_ptr[i * 4 + 2].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[2]); + list_ptr[i * 4 + 3].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[3]); + list_ptr[i * 4 + 0].vaddr = list_ptr[i * 4 + 0].vaddr; + list_ptr[i * 4 + 1].vaddr = list_ptr[i * 4 + 1].vaddr; + list_ptr[i * 4 + 2].vaddr = list_ptr[i * 4 + 2].vaddr; + list_ptr[i * 4 + 3].vaddr = list_ptr[i * 4 + 3].vaddr; + sg_ptr++; + } + + components = list_cnt % 4; + switch (components) { + case 3: + list_ptr[i * 4 + 2].size = rte_be_to_cpu_16(sg_ptr->u.s.len[2]); + list_ptr[i * 4 + 2].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[2]); + list_ptr[i * 4 + 2].vaddr = list_ptr[i * 4 + 2].vaddr; + /* FALLTHROUGH */ + case 2: + list_ptr[i * 4 + 1].size = rte_be_to_cpu_16(sg_ptr->u.s.len[1]); + list_ptr[i * 4 + 1].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[1]); + list_ptr[i * 4 + 1].vaddr = list_ptr[i * 4 + 1].vaddr; + /* FALLTHROUGH */ + case 1: + list_ptr[i * 4 + 0].size = rte_be_to_cpu_16(sg_ptr->u.s.len[0]); + list_ptr[i * 4 + 0].vaddr = (void *)rte_be_to_cpu_64(sg_ptr->ptr[0]); + list_ptr[i * 4 + 0].vaddr = list_ptr[i * 4 + 0].vaddr; + break; + default: + break; + } + + for (i = 0; i < list_cnt; i++) { + snprintf(suffix, sizeof(suffix), "%s[%d]: vaddr 0x%" PRIx64 ", vaddr %p len %u", + list, i, (uint64_t)list_ptr[i].vaddr, list_ptr[i].vaddr, list_ptr[i].size); + rte_hexdump(stdout, suffix, list_ptr[i].vaddr, list_ptr[i].size); + } +} +#endif + static __rte_always_inline int __rte_hot cpt_sec_tls_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, struct cn10k_sec_session *sess, struct cpt_inst_s *inst, @@ -205,6 +304,31 @@ cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[], struct inst[0].w7.u64 = w7; +#ifdef CPT_INST_DEBUG_ENABLE + infl_req->dptr = (uint8_t *)inst[0].dptr; + infl_req->rptr = (uint8_t *)inst[0].rptr; + infl_req->is_sg_ver2 = is_sg_ver2; + infl_req->scatter_sz = inst[0].w6.s.scatter_sz; + infl_req->opcode_major = inst[0].w4.s.opcode_major; + + rte_hexdump(stdout, "cptr", (void *)(uint64_t)inst[0].w7.s.cptr, 128); + printf("major opcode:%d\n", inst[0].w4.s.opcode_major); + printf("minor opcode:%d\n", inst[0].w4.s.opcode_minor); + printf("param1:%d\n", inst[0].w4.s.param1); + printf("param2:%d\n", inst[0].w4.s.param2); + printf("dlen:%d\n", inst[0].w4.s.dlen); + + if (is_sg_ver2) { + cpt_request_data_sgv2_mode_dump((void *)inst[0].dptr, 1, inst[0].w5.s.gather_sz); + cpt_request_data_sgv2_mode_dump((void *)inst[0].rptr, 0, inst[0].w6.s.scatter_sz); + } else { + if (infl_req->opcode_major >> 7) { + cpt_request_data_sg_mode_dump((void *)inst[0].dptr, 1); + cpt_request_data_sg_mode_dump((void *)inst[0].dptr, 0); + } + } +#endif + return 1; } @@ -935,6 +1059,15 @@ cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, struct rte_crypto_op *cop } if (likely(compcode == CPT_COMP_GOOD)) { +#ifdef CPT_INST_DEBUG_ENABLE + if (infl_req->is_sg_ver2) + cpt_request_data_sgv2_mode_dump(infl_req->rptr, 0, infl_req->scatter_sz); + else { + if (infl_req->opcode_major >> 7) + cpt_request_data_sg_mode_dump(infl_req->dptr, 0); + } +#endif + if (unlikely(uc_compcode)) { if (uc_compcode == ROC_SE_ERR_GC_ICV_MISCOMPARE) cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h index c6bb8023ea..e7bba25cb8 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h @@ -51,6 +51,13 @@ struct cpt_inflight_req { }; void *mdata; uint8_t op_flags; +#ifdef CPT_INST_DEBUG_ENABLE + uint8_t scatter_sz; + uint8_t opcode_major; + uint8_t is_sg_ver2; + uint8_t *dptr; + uint8_t *rptr; +#endif void *qp; } __rte_aligned(ROC_ALIGN); -- 2.25.1