From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53553438E9; Wed, 17 Jan 2024 11:32:13 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F23BB40ED6; Wed, 17 Jan 2024 11:31:36 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 8934940ED1 for ; Wed, 17 Jan 2024 11:31:35 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40H7jMDO028463 for ; Wed, 17 Jan 2024 02:31:34 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=Wv2/vcWtLrKPO++fLhkLGugM6aZYNlkG1IpKk8ZHB5E=; b=FcO uEcIWzGtfMPYYdXm+e07uHD3JSL9wVucMBR0o01xDCKOTotYKVpXBkGGWL5en1o5 h0u1ESvs7z3xSwJkqqijNBoAgwByBDKYPhYJguDPSetADDYhb5ZFfBB1JRi5GsP2 4rqgVmhc701zp3NxOOjFHRj5I3ejn1APKUO6UJrUdIR5m15FSFlFZ2j6sou4y4L0 jC7K7aiwk+q6dNnMTHeemt3fqiNJ9N1IfD1soMfcJnffqexZJ0FXIr0VtiF88RID evJpHzZj2BXRU9G60U58T2iF30GDmHJ2qAxEBuP0pvyqmr4vdn2GD3fALJl43y0W 2YBtyCu4kcR78uTQmzw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3vpask8f73-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 17 Jan 2024 02:31:34 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 17 Jan 2024 02:31:32 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 17 Jan 2024 02:31:32 -0800 Received: from BG-LT92004.corp.innovium.com (unknown [10.28.22.179]) by maili.marvell.com (Postfix) with ESMTP id D786F5B6931; Wed, 17 Jan 2024 02:31:30 -0800 (PST) From: Anoob Joseph To: Akhil Goyal CC: Rahul Bhansali , Jerin Jacob , Vidya Sagar Velumuri , Tejasree Kondoj , Subject: [PATCH v3 08/24] common/cnxk: add Rx inject configs Date: Wed, 17 Jan 2024 16:00:53 +0530 Message-ID: <20240117103109.922-9-anoobj@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240117103109.922-1-anoobj@marvell.com> References: <20240102045417.115-1-anoobj@marvell.com> <20240117103109.922-1-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: WF-uWoj0XLwPCm6oK4iwsTgxJQJFN3QH X-Proofpoint-GUID: WF-uWoj0XLwPCm6oK4iwsTgxJQJFN3QH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-17_05,2024-01-17_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rahul Bhansali Add Rx inject config for feature enable/disable, and store Rx chan value per port. Signed-off-by: Rahul Bhansali --- drivers/common/cnxk/roc_idev.c | 44 +++++++++++++++++++++++++++++ drivers/common/cnxk/roc_idev.h | 5 ++++ drivers/common/cnxk/roc_idev_priv.h | 6 ++++ drivers/common/cnxk/roc_nix.c | 2 ++ drivers/common/cnxk/version.map | 4 +++ 5 files changed, 61 insertions(+) diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c index e6c6b34d78..48df3518b0 100644 --- a/drivers/common/cnxk/roc_idev.c +++ b/drivers/common/cnxk/roc_idev.c @@ -310,3 +310,47 @@ roc_idev_nix_inl_meta_aura_get(void) return idev->inl_cfg.meta_aura; return 0; } + +uint8_t +roc_idev_nix_rx_inject_get(uint16_t port) +{ + struct idev_cfg *idev; + + idev = idev_get_cfg(); + if (idev != NULL && port < PLT_MAX_ETHPORTS) + return idev->inl_rx_inj_cfg.rx_inject_en[port]; + + return 0; +} + +void +roc_idev_nix_rx_inject_set(uint16_t port, uint8_t enable) +{ + struct idev_cfg *idev; + + idev = idev_get_cfg(); + if (idev != NULL && port < PLT_MAX_ETHPORTS) + __atomic_store_n(&idev->inl_rx_inj_cfg.rx_inject_en[port], enable, + __ATOMIC_RELEASE); +} + +uint16_t * +roc_idev_nix_rx_chan_base_get(void) +{ + struct idev_cfg *idev = idev_get_cfg(); + + if (idev != NULL) + return (uint16_t *)&idev->inl_rx_inj_cfg.chan; + + return NULL; +} + +void +roc_idev_nix_rx_chan_set(uint16_t port, uint16_t chan) +{ + struct idev_cfg *idev; + + idev = idev_get_cfg(); + if (idev != NULL && port < PLT_MAX_ETHPORTS) + __atomic_store_n(&idev->inl_rx_inj_cfg.chan[port], chan, __ATOMIC_RELEASE); +} diff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h index aea7f5279d..00664eaed6 100644 --- a/drivers/common/cnxk/roc_idev.h +++ b/drivers/common/cnxk/roc_idev.h @@ -22,4 +22,9 @@ struct roc_nix_list *__roc_api roc_idev_nix_list_get(void); struct roc_mcs *__roc_api roc_idev_mcs_get(uint8_t mcs_idx); void __roc_api roc_idev_mcs_set(struct roc_mcs *mcs); void __roc_api roc_idev_mcs_free(struct roc_mcs *mcs); + +uint8_t __roc_api roc_idev_nix_rx_inject_get(uint16_t port); +void __roc_api roc_idev_nix_rx_inject_set(uint16_t port, uint8_t enable); +uint16_t *__roc_api roc_idev_nix_rx_chan_base_get(void); +void __roc_api roc_idev_nix_rx_chan_set(uint16_t port, uint16_t chan); #endif /* _ROC_IDEV_H_ */ diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h index 80f8465e1c..8dc1cb25bf 100644 --- a/drivers/common/cnxk/roc_idev_priv.h +++ b/drivers/common/cnxk/roc_idev_priv.h @@ -19,6 +19,11 @@ struct idev_nix_inl_cfg { uint32_t refs; }; +struct idev_nix_inl_rx_inj_cfg { + uint16_t chan[PLT_MAX_ETHPORTS]; + uint8_t rx_inject_en[PLT_MAX_ETHPORTS]; +}; + struct idev_cfg { uint16_t sso_pf_func; uint16_t npa_pf_func; @@ -35,6 +40,7 @@ struct idev_cfg { struct nix_inl_dev *nix_inl_dev; struct idev_nix_inl_cfg inl_cfg; struct roc_nix_list roc_nix_list; + struct idev_nix_inl_rx_inj_cfg inl_rx_inj_cfg; plt_spinlock_t nix_inl_dev_lock; plt_spinlock_t npa_dev_lock; }; diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index f64933a1d9..97c0ae3e25 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -223,6 +223,8 @@ roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq, nix->nb_rx_queues = nb_rxq; nix->nb_tx_queues = nb_txq; + roc_idev_nix_rx_chan_set(roc_nix->port_id, rsp->rx_chan_base); + nix->rqs = plt_zmalloc(sizeof(struct roc_nix_rq *) * nb_rxq, 0); if (!nix->rqs) { rc = -ENOMEM; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index aa884a8fe2..f84382c401 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -105,6 +105,10 @@ INTERNAL { roc_idev_num_lmtlines_get; roc_idev_nix_inl_meta_aura_get; roc_idev_nix_list_get; + roc_idev_nix_rx_chan_base_get; + roc_idev_nix_rx_chan_set; + roc_idev_nix_rx_inject_get; + roc_idev_nix_rx_inject_set; roc_ml_reg_read64; roc_ml_reg_write64; roc_ml_reg_read32; -- 2.25.1