From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9085B439CC; Fri, 26 Jan 2024 07:14:13 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4346D42D68; Fri, 26 Jan 2024 07:14:13 +0100 (CET) Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by mails.dpdk.org (Postfix) with ESMTP id 11BA240289 for ; Fri, 26 Jan 2024 07:14:06 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4TLnS61WZ8zNlZr; Fri, 26 Jan 2024 14:13:10 +0800 (CST) Received: from dggpeml500024.china.huawei.com (unknown [7.185.36.10]) by mail.maildlp.com (Postfix) with ESMTPS id 0A4DC1402CD; Fri, 26 Jan 2024 14:14:05 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 26 Jan 2024 14:14:04 +0800 From: Chengwen Feng To: , , , CC: Subject: [PATCH v3 1/8] eal: introduce more macro for bit definition Date: Fri, 26 Jan 2024 06:10:06 +0000 Message-ID: <20240126061013.53608-2-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240126061013.53608-1-fengchengwen@huawei.com> References: <20231121122651.7078-1-fengchengwen@huawei.com> <20240126061013.53608-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500024.china.huawei.com (7.185.36.10) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Introduce macros: 1. RTE_SHIFT_VAL64: get the uint64_t value which shifted by nr. 2. RTE_SHIFT_VAL32: get the uint32_t value which shifted by nr. 3. RTE_GENMASK64: generate a contiguous 64bit bitmask starting at bit position low and ending at position high. 4. RTE_GENMASK32: generate a contiguous 32bit bitmask starting at bit position low and ending at position high. 5. RTE_FIELD_GET64: extract a 64bit field element. 6. RTE_FIELD_GET32: extract a 32bit field element. Signed-off-by: Chengwen Feng --- lib/eal/include/rte_bitops.h | 64 ++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index 6bd8bae21a..bab08d53ec 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -39,6 +39,70 @@ extern "C" { */ #define RTE_BIT32(nr) (UINT32_C(1) << (nr)) +/** + * Get the uint64_t value which shifted by nr. + * + * @param val + * The value to be shifted. + * @param nr + * The bit number in range of 0 to (64 - width of val). + */ +#define RTE_SHIFT_VAL64(val, nr) (UINT64_C(val) << (nr)) + +/** + * Get the uint32_t value which shifted by nr. + * + * @param val + * The value to be shifted. + * @param nr + * The bit number in range of 0 to (32 - width of val). + */ +#define RTE_SHIFT_VAL32(val, nr) (UINT32_C(val) << (nr)) + +/** + * Generate a contiguous 64bit bitmask starting at bit position low + * and ending at position high. + * + * @param high + * High bit position. + * @param low + * Low bit position. + */ +#define RTE_GENMASK64(high, low) (((~UINT64_C(0)) << (low)) & (~UINT64_C(0) >> (63u - (high)))) + +/** + * Generate a contiguous 32bit bitmask starting at bit position low + * and ending at position high. + * + * @param high + * High bit position. + * @param low + * Low bit position. + */ +#define RTE_GENMASK32(high, low) (((~UINT32_C(0)) << (low)) & (~UINT32_C(0) >> (31u - (high)))) + +/** + * Extract a 64bit field element. + * + * @param mask + * shifted mask. + * @param reg + * value of entire bitfield. + */ +#define RTE_FIELD_GET64(mask, reg) \ + ((typeof(mask))(((reg) & (mask)) >> rte_ctz64(mask))) + +/** + * Extract a 32bit field element. + * + * @param mask + * shifted mask. + * @param reg + * value of entire bitfield. + */ +#define RTE_FIELD_GET32(mask, reg) \ + ((typeof(mask))(((reg) & (mask)) >> rte_ctz32(mask))) + /*------------------------ 32-bit relaxed operations ------------------------*/ /** -- 2.17.1