From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2BC2843A53; Fri, 2 Feb 2024 20:34:42 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8384C42EC9; Fri, 2 Feb 2024 20:33:37 +0100 (CET) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2044.outbound.protection.outlook.com [40.107.220.44]) by mails.dpdk.org (Postfix) with ESMTP id 7FC3042EAF for ; Fri, 2 Feb 2024 20:33:34 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ifsDaUyiJOFmPBBDAj13LrGsce3hWjHbO22Ucf1A6ZXpcBjLSmkxlBGO47oYvde4yyAzVmB2X7OsQZ8t47C4MetSjP/zpiVB5yitRmrsExU6b5ENdS0ayklZIFD5SBlS+o3zskfGjzxffFadDcC1RO75t8yHo0EHy8GbvtNZRnUo5Cb/xqgXTDu/kBgQ0aKD42lLpgzIZercd2JT2OAVDt/1Jg90zCS3Q/p6ckadNW3Q4KO4YXa5b2p/3FxIc3O3Zi/FMaYdYXi2L8poIY2acIjfR3TZjxc6d9MPhDBMD6aX+oSNGZoKPqMGLaEgAEYcx++NbHjWicu5oVZ0G0xqiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JcnOjrbyu4LihqXjzacMaal0qjFuDCbwiRUeSyI8nxI=; b=ARIG4Gk85OHR61hLobzd4KVc+iChXTIURarGAdHwpJbjJL9Nyq6CYZG/sTvaccgFiRZqZSzKRTxcyYkOIXfSdB/FW1MkvbU5Xj4XITKTA2TnEnLIQ/H1OFIB74EdaeAqp1Nu3a4wAcLE+/mT7gGUJNGF6qVuPztUuGuxNzHHcB/x3uqCs1ZNp48rwLPoxvMGXhFMlProtjruSfEakpy+V/vczNNn7ldA4GHlNkyRbSPcipiFomCUFSIR2cnCrSSwQ78O6eiMQUhujDLifcvHPGZpYXCwTL9cAvtSbgUVfnlop+Kwn06fDA/racWQ+s6l0C0lio0gb/2f7usiOSbO/A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=dpdk.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JcnOjrbyu4LihqXjzacMaal0qjFuDCbwiRUeSyI8nxI=; b=FRKZ6uNG8HiANKl9oOgz78Ip7hdmVMSa7m3LPUPf3TH9TTWqTj1+8wQsBhYysB1TmN5Bb+rv7XDVqtBWu0TgUJdHumpvsJddtI3tjJfVhMdiFFVThLbQtMjs4GzRVNGWJE77TFxCxKJAQpjPzd96XBGQhalzk6PpBA4+0PS+Ek8= Received: from DM6PR10CA0033.namprd10.prod.outlook.com (2603:10b6:5:60::46) by DM6PR12MB4314.namprd12.prod.outlook.com (2603:10b6:5:211::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.13; Fri, 2 Feb 2024 19:33:32 +0000 Received: from DS1PEPF0001708F.namprd03.prod.outlook.com (2603:10b6:5:60:cafe::e1) by DM6PR10CA0033.outlook.office365.com (2603:10b6:5:60::46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.22 via Frontend Transport; Fri, 2 Feb 2024 19:33:32 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0001708F.mail.protection.outlook.com (10.167.17.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Fri, 2 Feb 2024 19:33:32 +0000 Received: from driver-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 2 Feb 2024 13:33:30 -0600 From: Andrew Boyer To: CC: Andrew Boyer Subject: [PATCH 12/13] net/ionic: optimize device stop operation Date: Fri, 2 Feb 2024 11:32:37 -0800 Message-ID: <20240202193238.62669-13-andrew.boyer@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240202193238.62669-1-andrew.boyer@amd.com> References: <20240202193238.62669-1-andrew.boyer@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001708F:EE_|DM6PR12MB4314:EE_ X-MS-Office365-Filtering-Correlation-Id: a5ce3ed8-5786-4cc1-a7f4-08dc2425d722 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: smDOZoZU3aV8bTLhA+tM72fQWQLSxwD1kzC8b4NtdoV7e58GuEsx3oGAPHU23yqxKHrgD1P5v3W09p1XayHgwDVPBRpNJ2sE27xg0aLL85H+/vqaNgHpsh9Ykl1nJ92omXgsYdZBp4jJGV9MdRm+g8XlJkWGAXcrlqjLBRAG0czTPT5cV5QfqFXXBAvt5780ynVQUoi/ouqvgo7QimILj2iFAQOHaHKmwwVBtjfq8bg6MHrh0ngu0PUh+s6JeFBMnRqmp7FlF2+tlmgfWXMACgv2wxR/WGHM56vmkRK5MTQtiB7qo9vMwb1pVRKn1wQkpJ28cA8JpT3Isa8oMLi2nvTJ2f3z3QycULxFtArIThZnLuecEMkStzgQCJOEqnrRcgxHh++2bwDVdKWxlzD0DcuIaNb6+K+sx96oKGslnoZfyQ4Q+3OQ4WCBIdq7RhKldGFPcbMrZeqlvX2+ejh5YaMFedPqSEF6lC9eYq4U7dtA6wOPuTnclzmAfJ2zY9iALZT5OPif/GEYBbp4LYDIyVlzCUb44goR7IYsH23k/++KF6j6mauWJMkqcvTPrBNf6v0MZXBKUSAhRAKSsnsLmLAtgvw5WaU0e11IoVZRJJbEnImF9H/OdHw0MuyNuaXpRLvFv5OYUddKZt645dFbcZSNKdtih2fBoVWn6XSQIUH/uiq7Ola03adoV/3xqN8+0XHZqUVTVuaRWXohSJIews6x4mdASI53/kt2KZKlMD19cwVVrur7pousWAW2hM3Pg8Q8QibobhzpLa2ukKZWWg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(346002)(136003)(376002)(396003)(39860400002)(230922051799003)(451199024)(186009)(64100799003)(82310400011)(1800799012)(40470700004)(36840700001)(46966006)(83380400001)(47076005)(336012)(81166007)(2616005)(426003)(26005)(1076003)(16526019)(356005)(82740400003)(36860700001)(44832011)(4326008)(8936002)(8676002)(5660300002)(2906002)(478600001)(70586007)(30864003)(6916009)(316002)(70206006)(86362001)(41300700001)(36756003)(40480700001)(40460700003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2024 19:33:32.0749 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5ce3ed8-5786-4cc1-a7f4-08dc2425d722 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4314 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Split the queue_stop operation into first-half and second-half helpers. Move the command context from the stack into each Rx/Tx queue struct. Expose some needed adminq interfaces. This allows us to batch up the queue commands during dev_stop(), reducing the outage window when restarting the process by about 1ms per queue. Signed-off-by: Andrew Boyer --- drivers/net/ionic/ionic.h | 3 ++ drivers/net/ionic/ionic_lif.c | 81 ++++++++++++++++++++++++---------- drivers/net/ionic/ionic_lif.h | 12 +++-- drivers/net/ionic/ionic_main.c | 17 ++++++- drivers/net/ionic/ionic_rxtx.c | 78 +++++++++++++++++++------------- drivers/net/ionic/ionic_rxtx.h | 14 +++++- 6 files changed, 143 insertions(+), 62 deletions(-) diff --git a/drivers/net/ionic/ionic.h b/drivers/net/ionic/ionic.h index c479eaba74..cb4ea450a9 100644 --- a/drivers/net/ionic/ionic.h +++ b/drivers/net/ionic/ionic.h @@ -83,7 +83,10 @@ struct ionic_admin_ctx { union ionic_adminq_comp comp; }; +int ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx); int ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx); +int ionic_adminq_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx); +uint16_t ionic_adminq_space_avail(struct ionic_lif *lif); int ionic_dev_cmd_wait_check(struct ionic_dev *idev, unsigned long max_wait); int ionic_setup(struct ionic_adapter *adapter); diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c index 90efcc8cbb..8ffdbc4df7 100644 --- a/drivers/net/ionic/ionic_lif.c +++ b/drivers/net/ionic/ionic_lif.c @@ -31,42 +31,54 @@ static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr); static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr); static int -ionic_qcq_disable(struct ionic_qcq *qcq) +ionic_qcq_disable_nowait(struct ionic_qcq *qcq, + struct ionic_admin_ctx *ctx) { + int err; + struct ionic_queue *q = &qcq->q; struct ionic_lif *lif = qcq->lif; - struct ionic_admin_ctx ctx = { - .pending_work = true, - .cmd.q_control = { - .opcode = IONIC_CMD_Q_CONTROL, - .type = q->type, - .index = rte_cpu_to_le_32(q->index), - .oper = IONIC_Q_DISABLE, - }, - }; - return ionic_adminq_post_wait(lif, &ctx); + memset(ctx, 0, sizeof(*ctx)); + ctx->pending_work = true; + ctx->cmd.q_control.opcode = IONIC_CMD_Q_CONTROL; + ctx->cmd.q_control.type = q->type; + ctx->cmd.q_control.index = rte_cpu_to_le_32(q->index); + ctx->cmd.q_control.oper = IONIC_Q_DISABLE; + + /* Does not wait for command completion */ + err = ionic_adminq_post(lif, ctx); + if (err) + ctx->pending_work = false; + return err; } void ionic_lif_stop(struct ionic_lif *lif) { - uint32_t i; + struct rte_eth_dev *dev = lif->eth_dev; + uint32_t i, j, chunk; IONIC_PRINT_CALL(); lif->state &= ~IONIC_LIF_F_UP; - for (i = 0; i < lif->nrxqcqs; i++) { - struct ionic_rx_qcq *rxq = lif->rxqcqs[i]; - if (rxq->flags & IONIC_QCQ_F_INITED) - (void)ionic_dev_rx_queue_stop(lif->eth_dev, i); + chunk = ionic_adminq_space_avail(lif); + + for (i = 0; i < lif->nrxqcqs; i += chunk) { + for (j = 0; j < chunk && i + j < lif->nrxqcqs; j++) + ionic_dev_rx_queue_stop_firsthalf(dev, i + j); + + for (j = 0; j < chunk && i + j < lif->nrxqcqs; j++) + ionic_dev_rx_queue_stop_secondhalf(dev, i + j); } - for (i = 0; i < lif->ntxqcqs; i++) { - struct ionic_tx_qcq *txq = lif->txqcqs[i]; - if (txq->flags & IONIC_QCQ_F_INITED) - (void)ionic_dev_tx_queue_stop(lif->eth_dev, i); + for (i = 0; i < lif->ntxqcqs; i += chunk) { + for (j = 0; j < chunk && i + j < lif->ntxqcqs; j++) + ionic_dev_tx_queue_stop_firsthalf(dev, i + j); + + for (j = 0; j < chunk && i + j < lif->ntxqcqs; j++) + ionic_dev_tx_queue_stop_secondhalf(dev, i + j); } } @@ -1240,21 +1252,42 @@ ionic_lif_rss_teardown(struct ionic_lif *lif) } void -ionic_lif_txq_deinit(struct ionic_tx_qcq *txq) +ionic_lif_txq_deinit_nowait(struct ionic_tx_qcq *txq) { - ionic_qcq_disable(&txq->qcq); + ionic_qcq_disable_nowait(&txq->qcq, &txq->admin_ctx); txq->flags &= ~IONIC_QCQ_F_INITED; } void -ionic_lif_rxq_deinit(struct ionic_rx_qcq *rxq) +ionic_lif_txq_stats(struct ionic_tx_qcq *txq) { - ionic_qcq_disable(&rxq->qcq); + struct ionic_tx_stats *stats = &txq->stats; + + IONIC_PRINT(DEBUG, "TX queue %u pkts %ju tso %ju", + txq->qcq.q.index, stats->packets, stats->tso); + IONIC_PRINT(DEBUG, "TX queue %u comps %ju (%ju per)", + txq->qcq.q.index, stats->comps, + stats->comps ? stats->packets / stats->comps : 0); +} + +void +ionic_lif_rxq_deinit_nowait(struct ionic_rx_qcq *rxq) +{ + ionic_qcq_disable_nowait(&rxq->qcq, &rxq->admin_ctx); rxq->flags &= ~IONIC_QCQ_F_INITED; } +void +ionic_lif_rxq_stats(struct ionic_rx_qcq *rxq) +{ + struct ionic_rx_stats *stats = &rxq->stats; + + IONIC_PRINT(DEBUG, "RX queue %u pkts %ju mtod %ju", + rxq->qcq.q.index, stats->packets, stats->mtods); +} + static void ionic_lif_adminq_deinit(struct ionic_lif *lif) { diff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h index cac7a4583b..ee13f5b7c8 100644 --- a/drivers/net/ionic/ionic_lif.h +++ b/drivers/net/ionic/ionic_lif.h @@ -10,7 +10,7 @@ #include #include -#include "ionic_osdep.h" +#include "ionic.h" #include "ionic_dev.h" #include "ionic_rx_filter.h" @@ -99,6 +99,8 @@ struct ionic_rx_qcq { /* cacheline4+ */ struct rte_mbuf *mbs[IONIC_MBUF_BULK_ALLOC] __rte_cache_aligned; + + struct ionic_admin_ctx admin_ctx; }; struct ionic_tx_qcq { @@ -112,6 +114,8 @@ struct ionic_tx_qcq { uint16_t flags; struct ionic_tx_stats stats; + + struct ionic_admin_ctx admin_ctx; }; #define IONIC_Q_TO_QCQ(_q) container_of(_q, struct ionic_qcq, q) @@ -225,10 +229,12 @@ int ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, void ionic_qcq_free(struct ionic_qcq *qcq); int ionic_lif_rxq_init(struct ionic_rx_qcq *rxq); -void ionic_lif_rxq_deinit(struct ionic_rx_qcq *rxq); +void ionic_lif_rxq_deinit_nowait(struct ionic_rx_qcq *rxq); +void ionic_lif_rxq_stats(struct ionic_rx_qcq *rxq); int ionic_lif_txq_init(struct ionic_tx_qcq *txq); -void ionic_lif_txq_deinit(struct ionic_tx_qcq *txq); +void ionic_lif_txq_deinit_nowait(struct ionic_tx_qcq *txq); +void ionic_lif_txq_stats(struct ionic_tx_qcq *txq); int ionic_lif_rss_config(struct ionic_lif *lif, const uint16_t types, const uint8_t *key, const uint32_t *indir); diff --git a/drivers/net/ionic/ionic_main.c b/drivers/net/ionic/ionic_main.c index c957d55bf9..1f24f64a33 100644 --- a/drivers/net/ionic/ionic_main.c +++ b/drivers/net/ionic/ionic_main.c @@ -180,6 +180,12 @@ ionic_adminq_service(struct ionic_cq *cq, uint16_t cq_desc_index, return true; } +uint16_t +ionic_adminq_space_avail(struct ionic_lif *lif) +{ + return ionic_q_space_avail(&lif->adminqcq->qcq.q); +} + /** ionic_adminq_post - Post an admin command. * @lif: Handle to lif. * @cmd_ctx: Api admin command context. @@ -191,7 +197,7 @@ ionic_adminq_service(struct ionic_cq *cq, uint16_t cq_desc_index, * * Return: zero or negative error status. */ -static int +int ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) { struct ionic_queue *q = &lif->adminqcq->qcq.q; @@ -279,7 +285,6 @@ ionic_adminq_wait_for_completion(struct ionic_lif *lif, int ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) { - bool done; int err; IONIC_PRINT(DEBUG, "Sending %s (%d) via the admin queue", @@ -292,6 +297,14 @@ ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) return err; } + return ionic_adminq_wait(lif, ctx); +} + +int +ionic_adminq_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) +{ + bool done; + done = ionic_adminq_wait_for_completion(lif, ctx, IONIC_DEVCMD_TIMEOUT); diff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c index d92fa1cca7..774dc596c0 100644 --- a/drivers/net/ionic/ionic_rxtx.c +++ b/drivers/net/ionic/ionic_rxtx.c @@ -92,36 +92,40 @@ ionic_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid) } int __rte_cold -ionic_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) +ionic_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) { - struct ionic_tx_stats *stats; - struct ionic_tx_qcq *txq; + ionic_dev_tx_queue_stop_firsthalf(dev, tx_queue_id); + ionic_dev_tx_queue_stop_secondhalf(dev, tx_queue_id); + + return 0; +} + +void __rte_cold +ionic_dev_tx_queue_stop_firsthalf(struct rte_eth_dev *dev, + uint16_t tx_queue_id) +{ + struct ionic_tx_qcq *txq = dev->data->tx_queues[tx_queue_id]; IONIC_PRINT(DEBUG, "Stopping TX queue %u", tx_queue_id); - txq = eth_dev->data->tx_queues[tx_queue_id]; + dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; - eth_dev->data->tx_queue_state[tx_queue_id] = - RTE_ETH_QUEUE_STATE_STOPPED; + ionic_lif_txq_deinit_nowait(txq); +} - /* - * Note: we should better post NOP Tx desc and wait for its completion - * before disabling Tx queue - */ +void __rte_cold +ionic_dev_tx_queue_stop_secondhalf(struct rte_eth_dev *dev, + uint16_t tx_queue_id) +{ + struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(dev); + struct ionic_tx_qcq *txq = dev->data->tx_queues[tx_queue_id]; - ionic_lif_txq_deinit(txq); + ionic_adminq_wait(lif, &txq->admin_ctx); /* Free all buffers from descriptor ring */ ionic_tx_empty(txq); - stats = &txq->stats; - IONIC_PRINT(DEBUG, "TX queue %u pkts %ju tso %ju", - txq->qcq.q.index, stats->packets, stats->tso); - IONIC_PRINT(DEBUG, "TX queue %u comps %ju (%ju per)", - txq->qcq.q.index, stats->comps, - stats->comps ? stats->packets / stats->comps : 0); - - return 0; + ionic_lif_txq_stats(txq); } int __rte_cold @@ -726,28 +730,40 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) * Stop Receive Units for specified queue. */ int __rte_cold -ionic_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) +ionic_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id) { - uint8_t *rx_queue_state = eth_dev->data->rx_queue_state; - struct ionic_rx_stats *stats; - struct ionic_rx_qcq *rxq; + ionic_dev_rx_queue_stop_firsthalf(dev, rx_queue_id); + ionic_dev_rx_queue_stop_secondhalf(dev, rx_queue_id); + + return 0; +} + +void __rte_cold +ionic_dev_rx_queue_stop_firsthalf(struct rte_eth_dev *dev, + uint16_t rx_queue_id) +{ + struct ionic_rx_qcq *rxq = dev->data->rx_queues[rx_queue_id]; IONIC_PRINT(DEBUG, "Stopping RX queue %u", rx_queue_id); - rxq = eth_dev->data->rx_queues[rx_queue_id]; + dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; + + ionic_lif_rxq_deinit_nowait(rxq); +} - rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; +void __rte_cold +ionic_dev_rx_queue_stop_secondhalf(struct rte_eth_dev *dev, + uint16_t rx_queue_id) +{ + struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(dev); + struct ionic_rx_qcq *rxq = dev->data->rx_queues[rx_queue_id]; - ionic_lif_rxq_deinit(rxq); + ionic_adminq_wait(lif, &rxq->admin_ctx); /* Free all buffers from descriptor ring */ ionic_rx_empty(rxq); - stats = &rxq->stats; - IONIC_PRINT(DEBUG, "RX queue %u pkts %ju mtod %ju", - rxq->qcq.q.index, stats->packets, stats->mtods); - - return 0; + ionic_lif_rxq_stats(rxq); } int diff --git a/drivers/net/ionic/ionic_rxtx.h b/drivers/net/ionic/ionic_rxtx.h index 5348395956..7ca23178cc 100644 --- a/drivers/net/ionic/ionic_rxtx.h +++ b/drivers/net/ionic/ionic_rxtx.h @@ -37,14 +37,24 @@ int ionic_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, const struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp); void ionic_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); int ionic_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); -int ionic_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id); +int ionic_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); int ionic_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, uint16_t nb_desc, uint32_t socket_id, const struct rte_eth_txconf *tx_conf); void ionic_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid); -int ionic_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id); int ionic_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); +int ionic_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); + +/* Helpers for optimized dev_stop() */ +void ionic_dev_rx_queue_stop_firsthalf(struct rte_eth_dev *dev, + uint16_t rx_queue_id); +void ionic_dev_rx_queue_stop_secondhalf(struct rte_eth_dev *dev, + uint16_t rx_queue_id); +void ionic_dev_tx_queue_stop_firsthalf(struct rte_eth_dev *dev, + uint16_t tx_queue_id); +void ionic_dev_tx_queue_stop_secondhalf(struct rte_eth_dev *dev, + uint16_t tx_queue_id); void ionic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, struct rte_eth_rxq_info *qinfo); -- 2.17.1