From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C597E43B10; Wed, 14 Feb 2024 21:15:12 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 756C142E9F; Wed, 14 Feb 2024 21:15:12 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 8C9A3400D5 for ; Wed, 14 Feb 2024 21:15:10 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D2D851FB; Wed, 14 Feb 2024 12:15:50 -0800 (PST) Received: from ampere-altra-2-1.usa.Arm.com (ampere-altra-2-1.usa.arm.com [10.118.91.158]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CE3803F7B4; Wed, 14 Feb 2024 12:15:09 -0800 (PST) From: Wathsala Vithanage To: Thomas Monjalon , Dariusz Sosnowski , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad Cc: dev@dpdk.org, nd@arm.com, Wathsala Vithanage , Honnappa Nagarahalli Subject: [PATCH v2] net/mlx5: enable PCI related counters Date: Wed, 14 Feb 2024 20:14:55 +0000 Message-Id: <20240214201455.1388720-1-wathsala.vithanage@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240209204142.1148790-1-wathsala.vithanage@arm.com> References: <20240209204142.1148790-1-wathsala.vithanage@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Versions of Mellanox NICs starting from CX5 have device counters related to PCI. These counters are helpful in debugging IO bottlenecks. For instance, the outbound_pci_stalled_rd and outbound_pci_stalled_wr counters can help with identifying NIC stalls due to insufficient PCI credits, which otherwise would have required a PCI analyzer or a sophisticated PCI root port with a PMU. Currently none of these are available in the MLX5 PMD even though ethtool is capable of reading some of them. Since PMD uses the same ioctl used by ethtool (SIOCETHTOOL) and reads via the kernel driver it is possible to add support with ease. There is one more PCI related counter and a device counter that aren't implemented in the Linux driver at the moment. These two are named outbound_pci_buffer_overflow and dev_out_of_buffer respectively. As per Nvidia's documentation these two counters can tell the number of packets dropped due to pci buffer overflow and the number of times the device owned queue had not enough buffers allocated. Signed-off-by: Wathsala Vithanage Reviewed-by: Honnappa Nagarahalli Acked-by: Viacheslav Ovsiienko Acked-by: Dariusz Sosnowski --- .mailmap | 1 + drivers/net/mlx5/linux/mlx5_ethdev_os.c | 41 +++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/.mailmap b/.mailmap index aa569ff456..f57415f7a1 100644 --- a/.mailmap +++ b/.mailmap @@ -1510,6 +1510,7 @@ Walter Heymans Wang Sheng-Hui Wangyu (Eric) Waterman Cao +Wathsala Vithanage Weichun Chen Wei Dai Weifeng Li diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index dd5a0c546d..c837c862a8 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -1574,6 +1574,47 @@ static const struct mlx5_counter_ctrl mlx5_counters_init[] = { .dpdk_name = "tx_vport_bytes", .ctr_name = "vport_tx_bytes", }, + /** + * Device counters: These counters are for the + * entire PCI device (NIC). These counters are + * not counting on a per port/queue basis. + * Values reported by these counters may not be + * useful if the device is bifurcated and queues + * are shared with the kernel or other DPDK + * applications. + */ + { + .dpdk_name = "rx_pci_signal_integrity", + .ctr_name = "rx_pci_signal_integrity", + }, + { + .dpdk_name = "tx_pci_signal_integrity", + .ctr_name = "tx_pci_signal_integrity", + }, + { + .dpdk_name = "outbound_pci_buffer_overflow", + .ctr_name = "outbound_pci_buffer_overflow", + }, + { + .dpdk_name = "outbound_pci_stalled_rd", + .ctr_name = "outbound_pci_stalled_rd", + }, + { + .dpdk_name = "outbound_pci_stalled_wr", + .ctr_name = "outbound_pci_stalled_wr", + }, + { + .dpdk_name = "outbound_pci_stalled_rd_events", + .ctr_name = "outbound_pci_stalled_rd_events", + }, + { + .dpdk_name = "outbound_pci_stalled_wr_events", + .ctr_name = "outbound_pci_stalled_wr_events", + }, + { + .dpdk_name = "dev_out_of_buffer", + .ctr_name = "dev_out_of_buffer", + }, }; static const unsigned int xstats_n = RTE_DIM(mlx5_counters_init); -- 2.25.1