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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1PEPF000042AB.mail.protection.outlook.com (10.167.243.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Tue, 20 Feb 2024 14:11:05 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 20 Feb 2024 06:10:46 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 20 Feb 2024 06:10:43 -0800 From: Bing Zhao To: , , , , , , , , , , Subject: [PATCH v2 2/5] net/mlx5: fetch the available registers for NAT64 Date: Tue, 20 Feb 2024 16:10:05 +0200 Message-ID: <20240220141008.292641-3-bingz@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220141008.292641-1-bingz@nvidia.com> References: <20231227090731.2569427-1-bingz@nvidia.com> <20240220141008.292641-1-bingz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AB:EE_|IA1PR12MB8334:EE_ X-MS-Office365-Filtering-Correlation-Id: 0093d7db-752d-42dd-2119-08dc321dc73a X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8334 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org REG_C_6 is used as the 1st one and since it is reserved internally by default, there is no impact. The remaining 2 registers will be fetched from the available TAGs array from right to left. They will not be masked in the array due to the fact that not all the rules will use NAT64 action. Signed-off-by: Bing Zhao --- drivers/net/mlx5/mlx5.c | 9 +++++++++ drivers/net/mlx5/mlx5.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 881c42a97a..9c3b9946e3 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1644,6 +1644,15 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh) if (!!((1 << i) & masks)) reg->hw_avl_tags[j++] = mlx5_regc_value(i); } + /* + * Set the registers for NAT64 usage internally. REG_C_6 is always used. + * The other 2 registers will be fetched from right to left, at least 2 + * tag registers should be available. + */ + MLX5_ASSERT(j >= (MLX5_FLOW_NAT64_REGS_MAX - 1)); + reg->nat64_regs[0] = REG_C_6; + reg->nat64_regs[1] = reg->hw_avl_tags[j - 2]; + reg->nat64_regs[2] = reg->hw_avl_tags[j - 1]; } static void diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 5265d1aa1f..544cf35069 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1407,10 +1407,12 @@ struct mlx5_hws_cnt_svc_mng { }; #define MLX5_FLOW_HW_TAGS_MAX 12 +#define MLX5_FLOW_NAT64_REGS_MAX 3 struct mlx5_dev_registers { enum modify_reg aso_reg; enum modify_reg hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX]; + enum modify_reg nat64_regs[MLX5_FLOW_NAT64_REGS_MAX]; }; #if defined(HAVE_MLX5DV_DR) && \ -- 2.34.1