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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN2PEPF0000449E.mail.protection.outlook.com (10.167.243.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Tue, 20 Feb 2024 14:38:20 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 20 Feb 2024 06:38:03 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 20 Feb 2024 06:38:00 -0800 From: Bing Zhao To: , , , , , , , , , , Subject: [PATCH v3 3/5] net/mlx5: create NAT64 actions during configuration Date: Tue, 20 Feb 2024 16:37:29 +0200 Message-ID: <20240220143731.295140-4-bingz@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220143731.295140-1-bingz@nvidia.com> References: <20231227090731.2569427-1-bingz@nvidia.com> <20240220143731.295140-1-bingz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449E:EE_|BY5PR12MB4919:EE_ X-MS-Office365-Filtering-Correlation-Id: c4efd804-be6b-476f-4e57-08dc32219606 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4919 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The NAT64 DR actions can be shared among the tables. All these actions can be created during configuring the flow queues and saved for the future usage. Even the actions can be shared now, inside per each flow rule, the actual hardware resources are unique. Signed-off-by: Bing Zhao --- doc/guides/nics/features/mlx5.ini | 1 + doc/guides/nics/mlx5.rst | 10 ++++ doc/guides/rel_notes/release_24_03.rst | 7 +++ drivers/net/mlx5/mlx5.h | 6 +++ drivers/net/mlx5/mlx5_flow.h | 11 +++++ drivers/net/mlx5/mlx5_flow_dv.c | 4 +- drivers/net/mlx5/mlx5_flow_hw.c | 65 ++++++++++++++++++++++++++ 7 files changed, 103 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini index 30027f2ba1..81a7067cc3 100644 --- a/doc/guides/nics/features/mlx5.ini +++ b/doc/guides/nics/features/mlx5.ini @@ -117,6 +117,7 @@ mark = Y meter = Y meter_mark = Y modify_field = Y +nat64 = Y nvgre_decap = Y nvgre_encap = Y of_pop_vlan = Y diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index fa013b03bb..248e4e41fa 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -168,6 +168,7 @@ Features - Matching on represented port. - Matching on aggregated affinity. - Matching on random value. +- NAT64. Limitations @@ -824,6 +825,15 @@ Limitations - Only match with compare result between packet fields is supported. +- NAT64 action: + - Supported only with HW Steering enabled (``dv_flow_en`` = 2). + - FW version: at least ``XX.39.1002``. + - Supported only on non-root table. + - Actions order limitation should follow the modify fields action. + - The last 2 TAG registers will be used implicitly in address backup mode. + - Even if the action can be shared, new steering entries will be created per flow rule. It is recommended a single rule with NAT64 should be shared to reduce the duplication of entries. The default address and other fields covertion will be handled with NAT64 action. To support other address, new rule(s) with modify fields on the IP addresses should be created. + - TOS / Traffic Class is not supported now. + Statistics ---------- diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 619459baae..492c77ff4f 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -102,6 +102,11 @@ New Features * ``rte_flow_template_table_resize_complete()``. Complete table resize. +* **Added a flow action type for NAT64.** + + Added ``RTE_FLOW_ACTION_TYPE_NAT64`` to support offloading of header conversion + between IPv4 and IPv6. + * **Updated Atomic Rules' Arkville PMD.** * Added support for Atomic Rules' TK242 packet-capture family of devices @@ -133,6 +138,8 @@ New Features * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_SEQ_NUM`` flow action. * Added HW steering support for modify field ``RTE_FLOW_FIELD_ESP_PROTO`` flow action. + * Added support for ``RTE_FLOW_ACTION_TYPE_NAT64`` flow action in HW Steering flow engine. + Removed Items ------------- diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 544cf35069..1ad40e38e1 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1986,6 +1986,12 @@ struct mlx5_priv { struct mlx5_aso_mtr_pool *hws_mpool; /* HW steering's Meter pool. */ struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx; /**< HW steering templates used to create control flow rules. */ + /* + * The NAT64 action can be shared among matchers per domain. + * [0]: RTE_FLOW_NAT64_6TO4, [1]: RTE_FLOW_NAT64_4TO6 + * Todo: consider to add *_MAX macro. + */ + struct mlx5dr_action *action_nat64[MLX5DR_TABLE_TYPE_MAX][2]; #endif struct rte_eth_dev *shared_host; /* Host device for HW steering. */ uint16_t shared_refcnt; /* HW steering host reference counter. */ diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index a4d0ff7b13..af41fd2112 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -159,6 +159,17 @@ struct mlx5_rte_flow_item_sq { uint32_t queue; /* DevX SQ number */ }; +/* Map from registers to modify fields. */ +extern enum mlx5_modification_field reg_to_field[]; +extern const size_t mlx5_mod_reg_size; + +static __rte_always_inline enum mlx5_modification_field +mlx5_convert_reg_to_field(enum modify_reg reg) +{ + MLX5_ASSERT((size_t)reg < mlx5_mod_reg_size); + return reg_to_field[reg]; +} + /* Feature name to allocate metadata register. */ enum mlx5_feature_name { MLX5_HAIRPIN_RX, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 6fded15d91..17c405508d 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -968,7 +968,7 @@ flow_dv_convert_action_modify_tcp_ack MLX5_MODIFICATION_TYPE_ADD, error); } -static enum mlx5_modification_field reg_to_field[] = { +enum mlx5_modification_field reg_to_field[] = { [REG_NON] = MLX5_MODI_OUT_NONE, [REG_A] = MLX5_MODI_META_DATA_REG_A, [REG_B] = MLX5_MODI_META_DATA_REG_B, @@ -986,6 +986,8 @@ static enum mlx5_modification_field reg_to_field[] = { [REG_C_11] = MLX5_MODI_META_REG_C_11, }; +const size_t mlx5_mod_reg_size = RTE_DIM(reg_to_field); + /** * Convert register set to DV specification. * diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 3bb3a9a178..386f6d1ae1 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -7606,6 +7606,66 @@ flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv) } } +static void +flow_hw_destroy_nat64_actions(struct mlx5_priv *priv) +{ + uint32_t i; + + for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) { + if (priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]) { + (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_6TO4]); + priv->action_nat64[i][RTE_FLOW_NAT64_6TO4] = NULL; + } + if (priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]) { + (void)mlx5dr_action_destroy(priv->action_nat64[i][RTE_FLOW_NAT64_4TO6]); + priv->action_nat64[i][RTE_FLOW_NAT64_4TO6] = NULL; + } + } +} + +static int +flow_hw_create_nat64_actions(struct mlx5_priv *priv, struct rte_flow_error *error) +{ + struct mlx5dr_action_nat64_attr attr; + uint8_t regs[MLX5_FLOW_NAT64_REGS_MAX]; + uint32_t i; + const uint32_t flags[MLX5DR_TABLE_TYPE_MAX] = { + MLX5DR_ACTION_FLAG_HWS_RX | MLX5DR_ACTION_FLAG_SHARED, + MLX5DR_ACTION_FLAG_HWS_TX | MLX5DR_ACTION_FLAG_SHARED, + MLX5DR_ACTION_FLAG_HWS_FDB | MLX5DR_ACTION_FLAG_SHARED, + }; + struct mlx5dr_action *act; + + attr.registers = regs; + /* Try to use 3 registers by default. */ + attr.num_of_registers = MLX5_FLOW_NAT64_REGS_MAX; + for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; i++) { + MLX5_ASSERT(priv->sh->registers.nat64_regs[i] != REG_NON); + regs[i] = mlx5_convert_reg_to_field(priv->sh->registers.nat64_regs[i]); + } + for (i = MLX5DR_TABLE_TYPE_NIC_RX; i < MLX5DR_TABLE_TYPE_MAX; i++) { + if (i == MLX5DR_TABLE_TYPE_FDB && !priv->sh->config.dv_esw_en) + continue; + attr.flags = (enum mlx5dr_action_nat64_flags) + (MLX5DR_ACTION_NAT64_V6_TO_V4 | MLX5DR_ACTION_NAT64_BACKUP_ADDR); + act = mlx5dr_action_create_nat64(priv->dr_ctx, &attr, flags[i]); + if (!act) + return rte_flow_error_set(error, rte_errno, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Failed to create v6 to v4 action."); + priv->action_nat64[i][RTE_FLOW_NAT64_6TO4] = act; + attr.flags = (enum mlx5dr_action_nat64_flags) + (MLX5DR_ACTION_NAT64_V4_TO_V6 | MLX5DR_ACTION_NAT64_BACKUP_ADDR); + act = mlx5dr_action_create_nat64(priv->dr_ctx, &attr, flags[i]); + if (!act) + return rte_flow_error_set(error, rte_errno, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Failed to create v4 to v6 action."); + priv->action_nat64[i][RTE_FLOW_NAT64_4TO6] = act; + } + return 0; +} + /** * Create an egress pattern template matching on source SQ. * @@ -9732,6 +9792,9 @@ flow_hw_configure(struct rte_eth_dev *dev, NULL, "Failed to VLAN actions."); goto err; } + if (flow_hw_create_nat64_actions(priv, error)) + DRV_LOG(WARNING, "Cannot create NAT64 action on port %u, " + "please check the FW version", dev->data->port_id); if (_queue_attr) mlx5_free(_queue_attr); if (port_attr->flags & RTE_FLOW_PORT_FLAG_STRICT_QUEUE) @@ -9764,6 +9827,7 @@ flow_hw_configure(struct rte_eth_dev *dev, } if (priv->hw_def_miss) mlx5dr_action_destroy(priv->hw_def_miss); + flow_hw_destroy_nat64_actions(priv); flow_hw_destroy_vlan(dev); if (dr_ctx) claim_zero(mlx5dr_context_close(dr_ctx)); @@ -9844,6 +9908,7 @@ flow_hw_resource_release(struct rte_eth_dev *dev) } if (priv->hw_def_miss) mlx5dr_action_destroy(priv->hw_def_miss); + flow_hw_destroy_nat64_actions(priv); flow_hw_destroy_vlan(dev); flow_hw_destroy_send_to_kernel_action(priv); flow_hw_free_vport_actions(priv); -- 2.34.1