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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000EE36.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Wed, 28 Feb 2024 10:26:08 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 28 Feb 2024 02:25:57 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 28 Feb 2024 02:25:53 -0800 From: Gregory Etelson To: CC: , , , Dariusz Sosnowski , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Matan Azrad , Rongwei Liu Subject: [PATCH v2 2/4] net/mlx5: fix parameters verification in HWS table create Date: Wed, 28 Feb 2024 12:25:24 +0200 Message-ID: <20240228102526.434717-3-getelson@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240228102526.434717-1-getelson@nvidia.com> References: <20240202115611.288892-2-getelson@nvidia.com> <20240228102526.434717-1-getelson@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE36:EE_|CH0PR12MB5140:EE_ X-MS-Office365-Filtering-Correlation-Id: adb36759-ed58-4f32-b909-08dc3847ad5b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2024 10:26:08.0039 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: adb36759-ed58-4f32-b909-08dc3847ad5b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5140 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Modified the conditionals in `flow_hw_table_create()` to use bitwise AND instead of equality checks when assessing `table_cfg->attr->specialize` bitmask. This will allow for greater flexibility as the bitmask may encapsulate multiple flags. The patch maintains the previous behavior with single flag values, while providing support for multiple flags. Fixes: 592d5367b5e4 ("net/mlx5: enable hint in async flow table") Signed-off-by: Gregory Etelson Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow_hw.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 783ad9e72a..5938d8b90c 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -4390,12 +4390,23 @@ flow_hw_table_create(struct rte_eth_dev *dev, matcher_attr.rule.num_log = rte_log2_u32(nb_flows); /* Parse hints information. */ if (attr->specialize) { - if (attr->specialize == RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG) - matcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_WIRE; - else if (attr->specialize == RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG) - matcher_attr.optimize_flow_src = MLX5DR_MATCHER_FLOW_SRC_VPORT; - else - DRV_LOG(INFO, "Unsupported hint value %x", attr->specialize); + uint32_t val = RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG | + RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG; + + if ((attr->specialize & val) == val) { + DRV_LOG(INFO, "Invalid hint value %x", + attr->specialize); + rte_errno = EINVAL; + goto it_error; + } + if (attr->specialize & + RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_WIRE_ORIG) + matcher_attr.optimize_flow_src = + MLX5DR_MATCHER_FLOW_SRC_WIRE; + else if (attr->specialize & + RTE_FLOW_TABLE_SPECIALIZE_TRANSFER_VPORT_ORIG) + matcher_attr.optimize_flow_src = + MLX5DR_MATCHER_FLOW_SRC_VPORT; } /* Build the item template. */ for (i = 0; i < nb_item_templates; i++) { -- 2.39.2