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(seliicwb00002.seli.gic.ericsson.se [10.156.25.100]) by seliicinfr00050.seli.gic.ericsson.se (Postfix) with ESMTP id CFE471C006A; Sat, 2 Mar 2024 15:02:12 +0100 (CET) From: =?UTF-8?q?Mattias=20R=C3=B6nnblom?= To: CC: , Heng Wang , =?UTF-8?q?Mattias=20R=C3=B6nnblom?= Subject: [RFC 0/7] Improve EAL bit operations API Date: Sat, 2 Mar 2024 14:53:21 +0100 Message-ID: <20240302135328.531940-1-mattias.ronnblom@ericsson.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00027A5E:EE_|PAWPR07MB9663:EE_ X-MS-Office365-Filtering-Correlation-Id: 664b9f25-b449-4118-8476-08dc3ac15c83 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uKUxUBM5uoT9EY6HWN46pM7Q/+9c+k9BHaIlxOA0MmknGprdLQX1U5wtsVE5/qdoKJUga+s+d3zt8pAwoc8Gcyf5EvMqd1ajjucz+vvUFPbwhhygzwBrGjCkZ2pbDEOLkIv1v7f4ZFLpqvbd0iHgo61V6QQ+v35Jm6HA2DR8IIVBhPzmwX02JaP3pTmM82/axRs0in/a1oXkny0Ft1eqHSzP4XDCGn9v2FplWY/lE99bRcMQucDrWnKdG7TfTaWkhNCAiqf5j8Bqrc3b0UdzZPUBJYqWe1jrENAw2jxGRCxsRHhNogiVgbJu++Kphq5GDOTY18LJj6AXK5chjGat7bwwD4suwOOmTD+I6/JtpQn/NNOu55Ap3/UsGpu82Ty/AJUq6Pv64qamq3lGiPR6y2ou2WEyF7xFfHLWJHalNtMgOib25aLEwhvK7AvO1WkxgZEcylRHoKRR4+m+o9xkfYJCh0BQdewAelTqfVEImSe/Nfab5AT5hF8VoDy9PE1FRAfb0hPuZdQrydo9PZCxzu3CX8lyasSeFBr7eHRIbPVzWkKRNAZ2XAFZOvXmHfB01JFG9KCcv2N3IGXHZ0NH2M1F5v/TXcYNKLWQuMcZ287uAZ5KwYA/xUYcyRzbGLtCDpQzQIjIHJgS32VZKaC+Tdcwl4ijV1TE0jidz485vG8qkjdKefn1OX0lcyo8Q85hX+LCVXVRzei5ine5CuKjPJ7OVrU7jXyjblIZgFgU0URCFGSBZAQ5LgDpXVeVImWY X-Forefront-Antispam-Report: CIP:192.176.1.74; CTRY:SE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:oa.msg.ericsson.com; PTR:office365.se.ericsson.net; CAT:NONE; SFS:(13230031)(376005)(36860700004)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: ericsson.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2024 14:02:13.4364 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 664b9f25-b449-4118-8476-08dc3ac15c83 X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=92e84ceb-fbfd-47ab-be52-080c6b87953f; Ip=[192.176.1.74]; Helo=[oa.msg.ericsson.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A5E.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR07MB9663 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch set represent an attempt to improve and extend the RTE bitops API, in particular for functions that operate on individual bits. RFCv1 is submitted primarily to 1) receive general feedback on if improvements in this area is worth working on, and 2) receive feedback on the API. No test cases are included in v1 and the various functions may well not do what they are intended to. The legacy rte_bit_relaxed_*() family of functions is replaced with three families: rte_bit_[test|set|clear|assign][32|64]() which provides no memory ordering or atomicity guarantees and no read-once or write-once semantics (e.g., no use of volatile), but does provide the best performance. The performance degradation resulting from the use of volatile (e.g., forcing loads and stores to actually occur and in the number specified) and atomic (e.g., LOCK instructions on x86) may be a significant. rte_bit_once_*() which guarantees program-level load and stores actually occurring (i.e., prevents certain optimizations). The primary use of these functions are in the context of memory mapped I/O. Feedback on the details (semantics, naming) here would be greatly appreciated, since the author is not much of a driver developer. rte_bit_atomic_*() which provides atomic bit-level operations, including the possibility to specifying memory ordering constraints (or the lack thereof). The atomic functions take non-_Atomic pointers, to be flexible, just like the GCC builtins and default . The issue with _Atomic APIs is that it may well be the case that the user wants to perform both non-atomic and atomic operations on the same word. Having _Atomic-marked addresses would complicate supporting atomic bit-level operations in the proposed bitset API (and potentially other APIs depending on RTE bitops for atomic bit-level ops). Either one needs two bitset variants, one _Atomic bitset and one non-atomic one, or the bitset code needs to cast the non-_Atomic pointer to an _Atomic one. Having a separate _Atomic bitset would be bloat and also prevent the user from both, in some situations, doing atomic operations against a bit set, while in other situations (e.g., at times when MT safety is not a concern) operating on the same words in a non-atomic manner. That said, all this is still unclear to the author and much depending on the future path of DPDK atomics. Unlike rte_bit_relaxed_*(), individual bits are represented by bool, not uint32_t or uint64_t. The author found the use of such large types confusing, and also failed to see any performance benefits. A set of functions rte_bit_*_assign*() are added, to assign a particular boolean value to a particular bit. All functions have properly documented semantics. All functions are available in uint32_t and uint64_t variants. In addition, for every function there is a generic selection variant which operates on both 32-bit and 64-bit words (depending on the pointer type). The use of C11 generic selection is the first in the DPDK code base. _Generic allow the user code to be a little more impact. Have a generic atomic test/set/clear/assign bit API also seems consistent with the "core" (word-size) atomics API, which is generic (both GCC builtins and are). The _Generic versions also may avoid having explicit unsigned long versions of all functions. If you have an unsigned long, it's safe to use the generic version (e.g., rte_set_bit()) and _Generic will pick the right function, provided long is either 32 or 64 bit on your platform (which it is on all DPDK-supported ABIs). The generic rte_bit_set() is a macro, and not a function, but nevertheless has been given a lower-case name. That's how C11 does it (for atomics, and other _Generic), and . Its address can't be taken, but it does not evaluate its parameters more than once. Things that are left out of this patch set, that may be included in future versions: * Have all functions returning a bit number have the same return type (i.e., unsigned int). * Harmonize naming of some GCC builtin wrappers (i.e., rte_fls_u32()). * Add __builtin_ffsll()/ffs() wrapper and potentially other wrappers for useful/used bit-level GCC builtins. * Eliminate the MSVC #ifdef-induced documentation duplication. * _Generic versions of things like rte_popcount32(). (?) ABI-breaking patches should probably go into a separate patch set (?). Mattias Rönnblom (7): eal: extend bit manipulation functions eal: add generic bit manipulation macros eal: add bit manipulation functions which read or write once eal: add generic once-type bit operations macros eal: add atomic bit operations eal: add generic atomic bit operations eal: deprecate relaxed family of bit operations lib/eal/include/rte_bitops.h | 1115 +++++++++++++++++++++++++++++++++- 1 file changed, 1113 insertions(+), 2 deletions(-) -- 2.34.1