* [PATCH] common/qat: fix undefined macro
@ 2024-03-05 11:55 Ciara Power
2024-03-05 12:08 ` Nayak, Nishikanta
2024-03-05 12:15 ` Ali Alnubani
0 siblings, 2 replies; 4+ messages in thread
From: Ciara Power @ 2024-03-05 11:55 UTC (permalink / raw)
To: dev; +Cc: gakhil, Ciara Power, nishikanta.nayak, Kai Ji
When using RTE_ENABLE_ASSERT and debug mode, an undefined
macro error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL.
This was not being defined, but is now added to the header file.
Bugzilla ID: 1395
Fixes: e9271821e489 ("common/qat: support GEN LCE device")
Signed-off-by: Ciara Power <ciara.power@intel.com>
---
Cc: nishikanta.nayak@intel.com
---
drivers/common/qat/qat_adf/icp_qat_fw_la.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
index 67fc25c919..fe32b66c50 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
@@ -111,6 +111,7 @@ struct icp_qat_fw_la_bulk_req {
#define ICP_QAT_FW_SYM_IV_IN_DESC_VALID 1
#define ICP_QAT_FW_SYM_DIRECTION_BITPOS 15
#define ICP_QAT_FW_SYM_DIRECTION_MASK 0x1
+#define ICP_QAT_FW_SYM_COMM_ADDR_SGL 1
/* In GEN_LCE AEAD AES GCM Algorithm has ID 0 */
#define QAT_LA_CRYPTO_AEAD_AES_GCM_GEN_LCE 0
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread* RE: [PATCH] common/qat: fix undefined macro
2024-03-05 11:55 [PATCH] common/qat: fix undefined macro Ciara Power
@ 2024-03-05 12:08 ` Nayak, Nishikanta
2024-03-05 12:15 ` Ali Alnubani
1 sibling, 0 replies; 4+ messages in thread
From: Nayak, Nishikanta @ 2024-03-05 12:08 UTC (permalink / raw)
To: Power, Ciara, dev; +Cc: gakhil, Ji, Kai
> -----Original Message-----
> From: Power, Ciara <ciara.power@intel.com>
> Sent: Tuesday, March 5, 2024 5:26 PM
> To: dev@dpdk.org
> Cc: gakhil@marvell.com; Power, Ciara <ciara.power@intel.com>; Nayak,
> Nishikanta <nishikanta.nayak@intel.com>; Ji, Kai <kai.ji@intel.com>
> Subject: [PATCH] common/qat: fix undefined macro
>
> When using RTE_ENABLE_ASSERT and debug mode, an undefined macro
> error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL.
> This was not being defined, but is now added to the header file.
>
> Bugzilla ID: 1395
> Fixes: e9271821e489 ("common/qat: support GEN LCE device")
>
> Signed-off-by: Ciara Power <ciara.power@intel.com>
>
> ---
> Cc: nishikanta.nayak@intel.com
> ---
> drivers/common/qat/qat_adf/icp_qat_fw_la.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> index 67fc25c919..fe32b66c50 100644
> --- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> +++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h
> @@ -111,6 +111,7 @@ struct icp_qat_fw_la_bulk_req { #define
> ICP_QAT_FW_SYM_IV_IN_DESC_VALID 1 #define
> ICP_QAT_FW_SYM_DIRECTION_BITPOS 15 #define
> ICP_QAT_FW_SYM_DIRECTION_MASK 0x1
> +#define ICP_QAT_FW_SYM_COMM_ADDR_SGL 1
>
> /* In GEN_LCE AEAD AES GCM Algorithm has ID 0 */ #define
> QAT_LA_CRYPTO_AEAD_AES_GCM_GEN_LCE 0
> --
> 2.25.1
Acked-by: Nishikant Nayak <nishikanta.nayak@intel.com>
^ permalink raw reply [flat|nested] 4+ messages in thread* RE: [PATCH] common/qat: fix undefined macro
2024-03-05 11:55 [PATCH] common/qat: fix undefined macro Ciara Power
2024-03-05 12:08 ` Nayak, Nishikanta
@ 2024-03-05 12:15 ` Ali Alnubani
2024-03-05 13:17 ` Thomas Monjalon
1 sibling, 1 reply; 4+ messages in thread
From: Ali Alnubani @ 2024-03-05 12:15 UTC (permalink / raw)
To: Ciara Power, dev; +Cc: gakhil, nishikanta.nayak, Kai Ji
> -----Original Message-----
> From: Ciara Power <ciara.power@intel.com>
> Sent: Tuesday, March 5, 2024 1:56 PM
> To: dev@dpdk.org
> Cc: gakhil@marvell.com; Ciara Power <ciara.power@intel.com>;
> nishikanta.nayak@intel.com; Kai Ji <kai.ji@intel.com>
> Subject: [PATCH] common/qat: fix undefined macro
>
> When using RTE_ENABLE_ASSERT and debug mode, an undefined
> macro error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL.
> This was not being defined, but is now added to the header file.
>
> Bugzilla ID: 1395
> Fixes: e9271821e489 ("common/qat: support GEN LCE device")
>
> Signed-off-by: Ciara Power <ciara.power@intel.com>
>
> ---
Can confirm it resolves the build failure, thanks!
Tested-by: Ali Alnubani <alialnu@nvidia.com>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] common/qat: fix undefined macro
2024-03-05 12:15 ` Ali Alnubani
@ 2024-03-05 13:17 ` Thomas Monjalon
0 siblings, 0 replies; 4+ messages in thread
From: Thomas Monjalon @ 2024-03-05 13:17 UTC (permalink / raw)
To: Ciara Power; +Cc: dev, gakhil, nishikanta.nayak, Kai Ji, Ali Alnubani
05/03/2024 13:15, Ali Alnubani:
> > -----Original Message-----
> > From: Ciara Power <ciara.power@intel.com>
> > Sent: Tuesday, March 5, 2024 1:56 PM
> > To: dev@dpdk.org
> > Cc: gakhil@marvell.com; Ciara Power <ciara.power@intel.com>;
> > nishikanta.nayak@intel.com; Kai Ji <kai.ji@intel.com>
> > Subject: [PATCH] common/qat: fix undefined macro
> >
> > When using RTE_ENABLE_ASSERT and debug mode, an undefined
> > macro error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL.
> > This was not being defined, but is now added to the header file.
> >
> > Bugzilla ID: 1395
> > Fixes: e9271821e489 ("common/qat: support GEN LCE device")
> >
> > Signed-off-by: Ciara Power <ciara.power@intel.com>
> >
> > ---
>
> Can confirm it resolves the build failure, thanks!
>
> Tested-by: Ali Alnubani <alialnu@nvidia.com>
Reported-by: Ali Alnubani <alialnu@nvidia.com>
Applied, thanks.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2024-03-05 13:17 UTC | newest]
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2024-03-05 11:55 [PATCH] common/qat: fix undefined macro Ciara Power
2024-03-05 12:08 ` Nayak, Nishikanta
2024-03-05 12:15 ` Ali Alnubani
2024-03-05 13:17 ` Thomas Monjalon
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