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Thu, 14 Mar 2024 04:43:30 -0700 From: Itamar Gozlan To: , , , , , , , Dariusz Sosnowski , Ori Kam , Suanming Mou , Matan Azrad CC: , Subject: [PATCH 13/13] net/mlx5/hws: fix port ID for root matcher and rule Date: Thu, 14 Mar 2024 13:42:20 +0200 Message-ID: <20240314114220.203241-13-igozlan@nvidia.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240314114220.203241-1-igozlan@nvidia.com> References: <20240314114220.203241-1-igozlan@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000009:EE_|IA0PR12MB9009:EE_ X-MS-Office365-Filtering-Correlation-Id: a011d9a4-0e16-4c20-f796-08dc441c0308 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ryyKoR0kTV8m2A8aIhYIo5ExkLyQQs5IgVlsBKpfd7V8rCkCPupDJmxkQXs7jV7bgVcRRUg0hOTC9qTkA2l4yXA7opqaTheZmcDaVSDVL+qi9idlvQ+RpXfPgqDonhXhUO7BxNWw0eGtDIEW+fJRT78MbNKPciG1oRA4hrRPz6/VdTioNeXU18y3oyvGnc+knvpDQ971Py9a2E7n2Wk81X6/OL482bCKV9Tmyt3q3QjHJqL2Xo4+LcmN/gYjTgBz/ALDlfiCsyOJmGDKPvkoOaoBjPwGSy1o4oecAGWUtydrrSkzf0QTxMzvNnP18fN/MVDTTI0rg0jut0Aor2hVVL+kGgw9UordA/6K1hiF1383c9liafP3K8Z6LUXeJ2zQ4GOlaPSmiBMcH2Wzcph3YI39OrXPYBKGzVWlBGQwun1qXqDuizh61g9t+OyKarSLoa2ThU2lWbYdp/TJonHyywLCEiPpV1WptMQwPk4Ams2bJRwvo34CyU6V7NcMQ7DkddZ26sHq+rLk4mMCIuujFxTR3xtF5TMZBtbFOc/jnNtL8GkuwFTGDmsLyKbW8WhdefwiDrHTc/X777EXt9os9FnKjgSD95wVDcA8cGLV5yoQM3TLfh0mrjGjS9r1evvrzzafjTTuC9vkCUnzHtSaL178lzEDUrAgbrrRZECMwca1s1pRirha0vO+oggW8v9Uu9phCFXFjl8Hnjj0OXJIswc72cSze2Qrx6Ib3a+s7arBS/TUg/vZpBCLHPlHWp9w1xMzeJ+mMSLb1/ZoJjNpng== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(1800799015)(82310400014)(376005)(36860700004)(921011); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Mar 2024 11:43:47.8897 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a011d9a4-0e16-4c20-f796-08dc441c0308 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000009.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB9009 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Erez Shitrit In root tables matcher and rule need to have their port-id, otherwise the translate function that done in dpdk layer will not get the right attributes. For that whenever the matcher is matching the source-port we need to get the relevant port-id before calling the translate function. Fixes: 405242c52dd5 ("net/mlx5/hws: add rule object") Signed-off-by: Erez Shitrit Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr_matcher.c | 17 +++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_rule.c | 18 ++++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 18 ++++++++++++++++++ 3 files changed, 53 insertions(+) diff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c index 78d525e578..394244b55b 100644 --- a/drivers/net/mlx5/hws/mlx5dr_matcher.c +++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c @@ -1227,6 +1227,7 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher) struct mlx5dv_flow_match_parameters *mask; struct mlx5_flow_attr flow_attr = {0}; struct rte_flow_error rte_error; + struct rte_flow_item *item; uint8_t match_criteria; int ret; @@ -1255,6 +1256,22 @@ static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher) return rte_errno; } + /* We need the port id in case of matching representor */ + item = matcher->mt[0].items; + while (item->type != RTE_FLOW_ITEM_TYPE_END) { + if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR || + item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { + ret = flow_hw_get_port_id_from_ctx(ctx, &flow_attr.port_id); + if (ret) { + DR_LOG(ERR, "Failed to get port id for dev %s", + ctx->ibv_ctx->device->name); + rte_errno = EINVAL; + return rte_errno; + } + } + ++item; + } + mask = simple_calloc(1, MLX5_ST_SZ_BYTES(fte_match_param) + offsetof(struct mlx5dv_flow_match_parameters, match_buf)); if (!mask) { diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c index d56677a1a5..5dae4f3442 100644 --- a/drivers/net/mlx5/hws/mlx5dr_rule.c +++ b/drivers/net/mlx5/hws/mlx5dr_rule.c @@ -692,10 +692,28 @@ static int mlx5dr_rule_create_root(struct mlx5dr_rule *rule, struct mlx5dv_flow_match_parameters *value; struct mlx5_flow_attr flow_attr = {0}; struct mlx5dv_flow_action_attr *attr; + const struct rte_flow_item *cur_item; struct rte_flow_error error; uint8_t match_criteria; int ret; + /* We need the port id in case of matching representor */ + cur_item = items; + while (cur_item->type != RTE_FLOW_ITEM_TYPE_END) { + if (cur_item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR || + cur_item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { + ret = flow_hw_get_port_id_from_ctx(rule->matcher->tbl->ctx, + &flow_attr.port_id); + if (ret) { + DR_LOG(ERR, "Failed to get port id for dev %s", + rule->matcher->tbl->ctx->ibv_ctx->device->name); + rte_errno = EINVAL; + return rte_errno; + } + } + ++cur_item; + } + attr = simple_calloc(num_actions, sizeof(*attr)); if (!attr) { rte_errno = ENOMEM; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 34b5e0f45b..e435a686fd 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -2001,6 +2001,24 @@ flow_hw_get_reg_id(struct rte_eth_dev *dev, #endif } +static __rte_always_inline int +flow_hw_get_port_id_from_ctx(void *dr_ctx, uint32_t *port_val) +{ + uint32_t port; + + MLX5_ETH_FOREACH_DEV(port, NULL) { + struct mlx5_priv *priv; + priv = rte_eth_devices[port].data->dev_private; + + if (priv->dr_ctx == dr_ctx) { + *port_val = port; + return 0; + } + } + + return -EINVAL; +} + /** * Get GENEVE TLV option FW information according type and class. * -- 2.39.3